1. Dracula Verification PDRACULA LOGLVS DRC-ERC Command File
LVS Command File
LPE Command File
Schematic
layout
CDL Out
GDS II Database
PDRACULA
CDL Netlist
LOGLVS
DRC/ERC
LVS
LVSLOGIC.DAT
LPE
SPICE01.DAT

2. Run Dracula LPE (I)
1. LPE netlist 的 node name 要跟 schematic 相對應，故工作目錄中應該含有以下三個檔案：
　MyCellName.db，LPE command file ( lpe.com ) 與 Schematic Netlist( CDL out 後的結果)
2.執行 LOGLVS 將 netlist 轉換成 LVSLOGIC.DAT
　此步驟於 LVS 中示範過，方法相同。
3.執行PDRACULA來Compile LPE command file(步驟和 DRC/ERC command file相同)
　(請確定前述的LVSLOGIC.DAT檔案已經產生)
[vlsi20]:~/Dracula3m/Lpe>PDRACULA
*******************************************************************************
*/N* DRACULA3 ( REV / SUN-4 S5R4 /GENDATE: 19-MAR-98/14 )
*** ( Copyright 1995, Cadence ) ***
*/N* EXEC TIME =13:45: DATE =13-APR HOSTNAME = vlsi20
:/g lpe.com n
:/f
** NOTE : NO OUTPUT NEEDED SO SETTING SUMMARY-ONLY=YES FOR THIS RUN ONLY
** CREATING : COMMAND FILE : jxrun.com
** NOTE : THIS JOB HAS STAGES
END OF DRACULA COMPILATIONS
* Mbytes allocated to the current process.
* Mbytes is still in use.
* THE END OF PROGRAM TIME = 13:46:27 DATE =13-APR-99 *

3. Run Dracula LPE (II)
3. 執行
在 compile 完 command file 後若無任何錯誤會產生一個 jxrun.com的可執行檔
[vlsi20]:~/Dracula3m/Lpe>jxrun.com > lep.log& Ã
4. 檢視
產生LPE file之前DRACULA會先做LPECHK(類似 LVS)，要LPECHK 正確無誤才會產生LPE file。
以下為所轉出的LPE file 之例子 *
* CADENCE/LPE SPICE FILE : SPICE01
* DATE : 13-APR-99
****** MOS XTOR PARAMETERS FROM : 7MOSPNET
*.EQUI CKIN=5 CLOCK=6 GND=0 NET18=9 NET22=8 NET23=7 NET37=13 NET42=19
* NET6=3 NET7=4 NET8=14 VDD=2
*.GLOBAL
.SUBCKT SPICE

4. Run Dracula LPE (III) * *----- TOTAL # OF MOS TRANSISTORS FOUND : 41
M NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=1.86P PS=5.50U
M NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=0.45P PS=1.95U
M NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=0.45P PS=1.95U
M NCH L=0.60U W=66.00U AD=59.95P PD=98.80U AS=52.80P PS=85.20U *
*----- TOTAL # OF MOS TRANSISTORS FOUND :
* COMMENTED : *不可以有COMMENTED 值存在*
* 有 COMMENT 表示 Layout 上的 MOS 與 Schematic 上的 MOS 沒有完全對應，應該找出錯誤，後再重做 LPE*
******* DIODE PARAMETERS FROM : 7DIOPNET
****** RESISTORS PARAMETERS FROM : 7RESXNET
*----- TOTAL # OF RESISTORS FOUND : 0
COMMENTED :
CC E-14 *所抽出的雜散電容*
CC E-13
CC E-14
CC E-14
CC E-15 .
*----- TOTAL # OF CAPS FOUND :
* COMMENTED :
.ENDS

5. Post Layout Simulation (post-sim)
Two Methods of
Post Layout Simulation (post-sim)
Layout Parameter Extraction (LPE)
[Spice Netlist]
EPIC
power mill
time mill
path mill
HSPICE

6. Post-Sim Using HSPICE Pre-Sim Spice file Post-Sim Spice file
Title--Optimize Buffer Size with Wire Load 160fF
.inc '/vlsi-proj/mtpv1/Spice/model0.6V2'
*Netlist
CC0 Z gnd! 3.9e-12 $[CP]
MM5 net19 net27 vdd! vdd! PM W=76.8e-6 L=600e-9 M=1.0
MM4 Z net19 vdd! vdd! PM W=315e-6 L=600e-9 M=1.0
MM2 net31 I vdd! vdd! PM W=4.8e-6 L=600e-9 M=1.0
MM0 net27 net31 vdd! vdd! PM W=19.2e-6 L=600e-9 M=1.0
MM7 net19 net27 gnd! gnd! NM W=38.4e-6 L=600e-9 M=1.0
MM6 Z net19 gnd! gnd! NM W=146e-6 L=600e-9 M=1.0
MM3 net31 I gnd! gnd! NM W=2.4e-6 L=600e-9 M=1.0
MM1 net27 net31 gnd! gnd! NM W=9.6e-6 L=600e-9 M=1.0
*Parameters
.param supply=3.3 freq=300MEG
+t_ini=2.0n t_rf=0.5n t_cycle='1/freq'
*+t_width='t_cycle-1.1n'
+t_width='(t_cycle-2*t_rf)/2'
*Independent/Dependent Power Supply
vpower vdd! gnd! supply
*Input Signal
vin I 0 pulse(0 supply t_ini t_rf t_rf t_width t_cycle) .
Title--Optimize Buffer Size with Wire Load 160fF
.inc '/vlsi-proj/mtpv1/Spice/model0.6V2'
*Netlist
CC0 Z gnd! 3.9e-12 $[CP]
M I NM L=0.60U W=4.80U AD=6.72P PD=12.40U AS=6.72P PS=12.40U
M75 vdd I 9 vdd PM L=0.60U W=12.20U AD=17.08P PD=27.20U AS=17.08P PS=27.20U
M NM L=0.60U W=19.60U AD=22.05P PD=38.40U AS=15.68P PS=26.00U
M71 vdd vdd PM L=0.60U W=48.00U AD=54.00P PD=81.00U AS=38.40P PS=54.40U
M NM L=0.60U W=66.00U AD=59.95P PD=98.80U AS=52.80P PS=85.20U
M58 vdd vdd PM L=0.60U W=159.60U AD=144.97P PD=208.00U AS=128.48P PS=185.20U
M NM L=0.60U W=136.00U AD=124.95P PD=184.70U AS=108.80P PS=148.80U
M47 vdd vdd PM L=0.60U W=480.00U AD=420.00P PD=614.00U AS=384.00P PS=492.80U
*Parameters
.param supply=3.3 freq=300MEG
+t_ini=2.0n t_rf=0.5n t_cycle='1/freq'
*+t_width='t_cycle-1.1n'
+t_width='(t_cycle-2*t_rf)/2'
*Independent/Dependent Power Supply
vpower vdd! gnd! supply