1. CMSIS C Support for PORT
MKL25Z4.h defines PORT_Type structure with a PCR field (array of 32 integers)
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /** Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /** Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /** Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
__IO uint32_t ISFR; /** Interrupt Status Flag Register, offset: 0xA0 */
} PORT_Type;

2. CMSIS C Support for PORT
Header file defines pointers to PORT_Type registers
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)

3. CMSIS C Support for PORT
Also defines macros and constants
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT)) &PORT_PCR_MUX_MASK)

4. CMSIS C Support for DAC /** DAC - Register Layout Typedef */
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0,
array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1,
} DAT[2];
uint8_t RESERVED_0[28];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type;

5. DAC - Peripheral instance base addresses
/* DAC - Peripheral instance base addresses */ /** Peripheral DAC0 base address */ #define DAC0_BASE (0x4003F000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE)

6. C0 Bit Fields
/* C0 Bit Fields */ #define DAC_C0_DACBBIEN_MASK 0x1u #define DAC_C0_DACBBIEN_SHIFT 0 #define DAC_C0_DACBTIEN_MASK 0x2u #define DAC_C0_DACBTIEN_SHIFT 1 #define DAC_C0_LPEN_MASK 0x8u #define DAC_C0_LPEN_SHIFT 3 #define DAC_C0_DACSWTRG_MASK 0x10u #define DAC_C0_DACSWTRG_SHIFT 4 #define DAC_C0_DACTRGSEL_MASK 0x20u #define DAC_C0_DACTRGSEL_SHIFT 5 #define DAC_C0_DACRFS_MASK 0x40u #define DAC_C0_DACRFS_SHIFT 6 #define DAC_C0_DACEN_MASK 0x80u #define DAC_C0_DACEN_SHIFT 7

7. DAC Control Register 0: DACx_C0
DACEN - DAC Enabled when 1
DACRFS - DAC reference voltage select
0: DACREF_1. Connected to VREFH
1: DACREF_2. Connected to VDDA
LPEN - low-power mode
0: High-speed mode. Fast (15 us settling time) but uses more power (up to 900 uA supply current)
1: Low-power mode. Slow (100 us settling time) but more power-efficient (up to 250 uA supply current)
Additional control registers used for buffered mode

8. DAC Control Register 1: DACx_C1
DACBFEN
0: Disable buffer mode
1: Enable buffer mode
DACBFMD - Buffer mode select
0: Normal mode (circular buffer)
1: One-time scan mode

9. DAC Control Register 2 DAC Control Register 2
DABFRP: Data Buffer Read Pointer
DACBFUP: DAC Buffer Upper limit

10. DAC Example
1 – Supply clock to DAC0 module and PORT E SIM->SCGC6 |= (1UL << SIM_SCGC6_DAC0_SHIFT); SIM->SCGC5 |= (1UL << SIM_SCGC5_PORTE_SHIFT); 2 – Select analog PORTE->PCR[DAC_POS] &= ~(PORT_PCR_MUX(7)); 3 – Enable DAC (use C0 register) – Also select Reference. Here select VDDA DAC0->C0 = (1 << DAC_C0_DACEN_SHIFT) | (1 << DAC_C0_DACRFS_SHIFT); 4 – Configure DAC. (Disable buffer mode) DAC0->C1 = 0; DAC0->C2 = 0; 5 – Write to DAC data register DAC0->DAT[0].DATH = SOME_DATA_H; DAC0->DAT[0].DATL = SOME_DATA_L;

11. COMPARATOR
/** CMP - Register Layout Typedef */ typedef struct { __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ } CMP_Type;

12. CMP - Peripheral instance base addresses
/* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define CMP0_BASE (0x u) /** Peripheral CMP0 base pointer */ #define CMP0 ((CMP_Type *)CMP0_BASE)

13. COMPARATOR
#define CMP_CR1_EN_MASK 0x1u #define CMP_CR1_EN_SHIFT 0 #define CMP_MUXCR_MSEL_MASK 0x7u #define CMP_MUXCR_MSEL_SHIFT 0 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK 0x38u #define CMP_MUXCR_PSEL_SHIFT 3 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) #define CMP_DACCR_DACEN_MASK 0x80u #define CMP_DACCR_DACEN_SHIFT 7 #define CMP_DACCR_VOSEL_MASK 0x3Fu #define CMP_DACCR_VOSEL_SHIFT 0 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) #define CMP_SCR_CFR_MASK 0x4u #define CMP_SCR_CFR_SHIFT 2 #define CMP_SCR_IEF_MASK 0x8u #define CMP_SCR_IEF_SHIFT 3 #define CMP_SCR_IER_MASK 0x10u #define CMP_SCR_IER_SHIFT 4 #define CMP_SCR_COUT_MASK 0x1u #define CMP_SCR_COUT_SHIFT 0

14. COMPARATOR EXAMPLE
1 - Set the clock and select analog SIM->SCGC4 |= (1UL << SIM_SCGC4_CMP_SHIFT); SIM->SCGC5 |= (1UL << SIM_SCGC5_PORTE_SHIFT); PORTE->PCR[DAC_POS] &= ~(PORT_PCR_MUX(7)); // Select analog 2 – Enable comparator (use CR1 register) // Enable Comparator CMP0->CR1 = (1 << CMP_CR1_EN_SHIFT); 3 - Select input channels (use MUXCR register) // Plus: channel 5 on Port E bit 29 // Minus: CMP DAC is channel 7 CMP0->MUXCR = (5 << CMP_MUXCR_PSEL_SHIFT) | (7 << CMP_MUXCR_MSEL_SHIFT); 4 - Set reference voltage for DAC at 32/64 = 1/2 VREFH CMP0->DACCR = (1 << CMP_DACCR_DACEN_SHIFT)|(32 << CMP_DACCR_VOSEL_SHIFT); 5 - Enable interrupt for Comparator (on both edges) use SCR register CMP0->SCR = (1 << CMP_SCR_IEF_SHIFT) | (1 << CMP_SCR_IER_SHIFT);

15. COMPARATOR EXAMPLE
Interrupt Request Number for CMP is CMP0_IRQn (16) NVIC_SetPriority(CMP0_IRQn, 128); NVIC_ClearPendingIRQ(CMP0_IRQn); NVIC_EnableIRQ(CMP0_IRQn); Use void CMP0_IRQHandler(void) { for ISR Use SCR register to check the edge if (CMP0->SCR & CMP_SCR_CFR_MASK) { // rising edge detected How to work without interrupts (polling)? if (CMP0->SCR & CMP_SCR_COUT_MASK) {