1. 10-1 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi EE 319K Introduction to Embedded Systems Lecture 10: Sampling, Analog-to-Digital Conversion

2. 10-2 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi Agenda  Recap  Local Variables  Stack frames  Recursion  Fixed-point numbers  LCD device driver (Lab 7)  Outline  Sampling, Nyquist theorem  Analog to Digital Conversion

3. 10-3 Analog to Digital Converter (ADC) Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

4. 10-4 Nyquist Theorem  A bandlimited analog signal that has been sampled can be perfectly reconstructed from an infinite sequence of samples if the sampling rate f s exceeds 2f max samples per second, where f max is the highest frequency in the original signal.  If the analog signal does contain frequency components larger than (1/2)f s, then there will be an aliasing error.  Aliasing is when the digital signal appears to have a different frequency than the original analog signal.  Valvano Postulate: If f max is the largest frequency component of the analog signal, then you must sample more than ten times f max in order for the reconstructed digital samples to look like the original signal when plotted on a voltage versus time graph. Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi http://www.ece.utexas.edu/~valvano/UTx319K/nyquist2.html

5. 10-5 Sampling (option 1)  200Hz signal sampled at 2000Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls

6. 10-6 Sampling (option 1)  1000Hz signal sampled at 2000Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls

7. 10-7 Sampling (option 1)  2200Hz signal sampled at 2000Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi This is aliasing http://www.ece.utexas.edu/~valvano/Volume1/Nyquist.xls

8. 10-8 Sampling (option 2)  100Hz signal sampled at 1600Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls

9. 10-9 Sampling (option 2)  A signal with DC, 100Hz and 400Hz sampled at 1600Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls

10. 10-10 Sampling (option 2)  1500Hz signal sampled at 1600Hz Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi This is aliasing http://www.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/FFT16.xls

11. 10-11 Analog to Digital Converter (ADC)  Successive approximation ADC  V IN is approximated as a static value in a sample and hold (S/H) circuit  the successive approximation register (SAR) is a counter that increments each clock as long as it is enabled by the comparator  the output of the SAR is fed to a DAC that generates a voltage for comparison with V IN  when the output of the DAC = V IN the value of SAR is the digital representation of V IN end of conversion Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

12. 10-12 Sample-And-Hold Circuit  Analog Input (AI) is sampled when the switch is closed and its value is held on the capacitor where it becomes the Analog Output (AO) S/H Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

13. 10-13 ADC on TM4C123  Sampling Range/Resolution  3.3V internal reference voltage  0x000 at 0 V input  0xFFF at 3.3 V  resolution = range/precision = 3.3V/4096 alternatives < 1mV Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

14. 10-14  Twelve analog input channels  Single-ended and differential-input configurations  On-chip internal temperature sensor  Sample rate up to one million samples/second 40 Hz  Flexible, configurable analog-to-digital conversion  Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs  Flexible trigger control  Controller (software) We will use software initiated trigger  Timers  Analog Comparators  PWM  GPIO  Hardware averaging of up to 64 samples for improved accuracy  Converter uses an internal 3V reference Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi ADC on TM4C123 PE2=Ain1 used for Lab 8, 9, 10

15. 10-15 ADC on TM4C123 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi Ain1 PE2 Software initiated Bit 3 is done flag Use sequencer 3 PE2=Ain1 used for Lab 8, 9, 10

16. 10-16 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi ADC on TM4C123 Twelve different pins can be used to sample analog inputs. PD4=Ain4 used for DLL testing PE2=Ain1 used for Lab 8, 9, 10 PE4=Ain9 used in book and ADCSWTrigger_4C123

17. 10-17 ADC on TM4C123  TM4C ADC registers Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

18. 10-18 ADC on TM4C123  TM4C123 ADC Operation  select rate  select sequencer  select trigger  select channel  select sample mode o0 not temperature o1 set completion flag o1 end sequence o0 not differential Speed bits in ADC0_PC_R EM3, EM2, EM1, and EM0 bits in ADC_EMUX_R Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi ADC0_SSCTL3_R = 0x06;

19. 10-19 ADC on TM4C123  Initialization  Enable ADC clock: set bit 0 in SYSCTL_RCGCADC_R  Set 125kHz ADC conversion speed: write 0x01 to ADC0_PC_R  Set sequencer priority: 0,1,2,3 in ADC0_SSPRI_R  Disable selected sequence 3: zero bit 3 of ADC0_ACTSS_R  Set software start trigger event: zero bits 15-12 of ADC0_EMUX_R  Set input source (0-11): write channel number in bits 3-0 of ADC0_SSMUX3_R (channel 9 is PE4, channel 1 is PE2)  Set sample control bits: write 0110 in bits 3-0 ADC0_SSCTL3_R to disable temp measurement, notify on sample complete, indicate single sample in sequence, and denote single-ended signal mode  Disable interrupts: zero bit 3 of ADC0_IM_R  Enable selected sequencer 3: set bit 3 of ADC0_ACTSS_R Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

20. 10-20 ADC on TM4C123 Channel 9 is PE4 void ADC0_InitSWTriggerSeq3_Ch9(void){ SYSCTL_RCGCGPIO_R |= 0x10; // 1) activate clock for Port E while((SYSCTL_PRGPIO_R&0x10) == 0){}; GPIO_PORTE_DIR_R &= ~0x10; // 2) make PE4 input GPIO_PORTE_AFSEL_R |= 0x10; // 3) enable alternate fun on PE4 GPIO_PORTE_DEN_R &= ~0x10; // 4) disable digital I/O on PE4 GPIO_PORTE_AMSEL_R |= 0x10; // 5) enable analog fun on PE4 SYSCTL_RCGCADC_R |= 0x01; // 6) activate ADC0 delay = SYSCTL_RCGCADC_R; // extra time to stabilize delay = SYSCTL_RCGCADC_R; ADC0_PC_R = 0x01; // 7) configure for 125K ADC0_SSPRI_R = 0x0123; // 8) Seq 3 is highest priority ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3 ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger ADC0_SSMUX3_R = (ADC0_SSMUX3_R&0xFFFFFFF0)+9; // 11) Ain9 (PE4) ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0 ADC0_IM_R &= ~0x0008; // 13) disable SS3 interrupts ADC0_ACTSS_R |= 0x0008; // 14) enable sample sequencer 3 } Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi Book shows Ain9=PE4 Lab 8, 9, 10 use Ain1=PE2

21. 10-21 ADC on TM4C123  Analog to digital conversion  Set software trigger oWrite to PSSI bit 3  Busy-Wait oRaw Interrupt Status = RIS bit 3 oPoll until sample complete  Read sample oRead from SSFIFO3  Clear sample complete flag oWrite to ISC bit 3 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

22. 10-22 //------------ADC_InSeq3------------ // Busy-wait analog to digital conversion // Input: none // Output: 12-bit result of ADC conversion uint32_t ADC0_InSeq3(void){ uint32_t data; ADC0_PSSI_R = 0x0008; while((ADC0_RIS_R&0x08)==0){}; data = ADC0_SSFIFO3_R&0xFFF; ADC0_ISC_R = 0x0008; return data; } ADC on TM4C123 Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi