2. FAILURE ANALYSIS SAMPLE PREPARATION TECHNIQUES- DEPROCESSING
WET ETCHING
MICROELECTRONICS ENGINEERING
KUKUM

3. DIE DEPROCESSING
FAILED SEMICONDUCTOR DIES (=INTEGRATED CIRCUITS, VLSI), NEED TO BE INVESTIGATED FOR THEIR CAUSE OF FAILURE !
==>stripping off the upper layers of the die to expose a defect site that is buried underneath these layers==> preparatory step for subsequent analysis

4. WET ETCHING
WET = LIQUID
ETCHING=REMOVAL OF MATERIAL

5. WET ETCHING Wet etching = generally isotropic ,
all directions same rate.
An etching process that is not isotropic is referred to as 'anisotropic.'

6. WET ETCHING
Selectivity , S,= ratio between the different etch rates of the etchant for different materials.
HF is not selective--> etch out almost all the layers on the die surface.
H2O2 = hydrogen peroxide is highly selective
--> etch out only the TiW layer on the die surface.
Etch Rate =rate of material removal (μm/min)
- function of concentration, agitation, temperature, density and porosity of the thin film or substrate,…
Etch Geometry ~ sidewall slope (degree of anisotropy)
Wet etching is always followed by a an acetone / alcohol rinse, which in turn is followed by a D.I. water rinse

7. WET ETCHING Advantages : 1)low cost 2) high reliability
3) high throughput
4) excellent selectivity (In most cases with respect to both mask and substrate materials).
Automated wet etching systems add even more advantages:
5) greater ease of use
6) higher reproducibility
7) better efficiency in the use of etchants.

8. WET ETCHING Disadvantages : 1) limited resolution
2) higher safety risks due to the direct chemical exposure of the personnel
3) high cost of etchants in some cases
4) problems related to the resist's loss of adhesion to the substrate
5) problems related to the formation of bubbles which inhibit the etching process where they are present
6) problems related to incomplete or non-uniform etching

9. WHEN THIS FAILS IT NEEDS TO BE REVERSE ENGINEERED!
Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,
Red = Diffusion, and Gray = Substrate

10. …which corresponds to…

11. …which comprises… Layers: Passivation 2 : 0.6 micron
Metal 2 :
- aluminum : 1.0 micron
- barrier : 0.15 micron
Interlevel dielectric :
- glass 3 : 0.25 micron
- glass 2 : 0.09 micron
- glass 1 : 0.15 micron
Metal 1 :
- cap : 0.05 micron (approximate)
- aluminum : 0.5 micron
- barrier : 0.1 micron
Intermediate (reflow)
glass : 0.6 micron
Nitride layer : 0.04 micron (approximate)
Oxide on poly : 0.07 micron (approximate)
Poly 2 : 0.28 micron
Poly 1 : 0.28 micron
Local oxide : 0.6 micron
N+ S/D diffusion : 0.25 micron
N+ program diffusion : 0.4 micron (approximate)
P+ S/D diffusion : 0.3 micron
N- well : 4.5 microns
Epi : 9.5 microns
Approximate mask count: 18

12. …and fabricated as below.
Fabrication process: Selective oxidation CMOS process employing twin-wells in a P-epi on a P substrate.
Final passivation: A layer of silicon-nitride over a layer of glass.
Metallization: Two levels of metal defined by dry-etch techniques. Both metal ayers consisted of silicon-doped aluminum. Metal 2 employed a titanium barrier. Metal 1 employed a titanium-nitride cap and barrier.
Interlevel dielectric: Interlevel dielectric consisted of several layers of glass and a filler SOG. Via cuts through these layers were defined by a two step etch.
Intermediate glass: The intermediate glass consisted of a layer of reflow glass probably BPSG over various densified oxides. Contact cuts were defined by a two step etch (no reflow following contact cuts). A thin layer of nitride was present beneath the reflow glass.
Polysilicon: Two layers of polysilicon (no silicide) was used. Poly 1 was used to form gates on the die while poly 2 was used exclusively in the cell array where it formed program lines.
Diffusions: Standard implanted N+ and P+ diffusions formed the sources/drains of transistors. Oxide sidewall spacers were used to provide the LDD spacing and were left in place. Although the 1280A used lightly doped N+ extensions, no suchfeatures were noted on this device.
Wells: twin-wells in an P-epi.
Programmable antifuse array: The antifuse array is processed with ACTEL'S PLICE (Programmable Low Impedance Circuit Element) technology. Each antifuse consists of very thin dielectric sandwiched between poly 2 program lines and an N+ program diffusion (as indicated by manufacturer's information). The antifuse isprogrammed by using a voltage to rupture the thin dielectric.

13. WHAT NEEDS WET ETCHING? Silicon nitride - passivation
Silicon Oxide - passivation / insulation
Aluminium - conductor
Silicon - substrate
Surface cleaning

14. SILICON NITRIDE (Si3N4)
Silicon nitride= sealing layer / protective coating = passivation layer
-end of the fabrication
-protects against moisture / contamination through chemical action, corrosion, or handling during packaging
-usually occurs as a double layer with oxide, in which it lies on top.
=>usually dry etched - better S of 3:1 over Si & SiO2
PRODUCTION
LPCVD - LOW PRESSURE CHEMICAL VAPOUR DEPOSITION
PEN - PLASMA ENHANCED NITRIDE
PON - PLASMA OXYNITRIDE / SILICON OXYNITRIDE

15. Si3N4Wet Etching
Bolide Etch=2.2 wt% ammonium bifluoride in propylene glycol at 800C (not available anymore)
- minimal Al attack.
- useful if plasma damage/alteration of part is suspected due to nitride removal in plasma etcher.
- isotropic and has minimal Al and SiO2 etch rate at 1500C.
PEN: A/min
LPCVD Si3N4: 72 A/min
PON: 960 A/min
SiO2: A/min (silicon dioxide = silica = glass)
Si: 32 A/min

16. Si3N4Wet Etching
85%, aq. Phosphoric acid C, commercial
- classic Si3N4etch,
- slower than Bolide and aggressively removes aluminum.
@1800C @1500C
PEN: 525-1,250 A/min PEN : A/min
LPCVD Si3N4: 100 A/min LPCVD Si3N4: 34 A/min
PON: 1000 A/min PON: 350 A/min
SiO2 : A/min SiO2 : 1-40 A/min
Si : <1A/min Si : <1A/min

17. Si3N4Wet Etching
1) 1–10% HF and treatment in a HF/glycerine mixture (1-3 molar solution of 48% HF in C
2) 1:60 or 1:20 HF:H2O A/min
3) BHF 1:2:2 HF:NH4F:H2O slow attack ﾐ but faster for silicon oxynitride
4) 1:5 or 1:9 HF:NH4F (40%) microns/second
5) 3:25 HF:NH4F.HF(sat) 50ml:50g:100ml:50ml HF:NH4F.HF:H2O:glycerin ﾐ glycerin provides more uniform removal
6) BOE HF:NH4F:H2O 18g:5g:100ml
7) NaOH:KHC8H4O4:H2O boiling 160 A/min, better with silicon oxynitride
8) 9g:25ml NaOH:H20 ﾐ boiling 160A/min
9) 18g:5g:100ml NaOH:(NH4)2S2O8:H2O ﾐ boiling 160 A/min
10) A) 5g:100ml NH4F.HF:H2O
B)1g:50ml:50ml I2:H2O:glycerin ﾐ mix A and B 1:1 when ready to use. RT 180 A/min

18. Silicon Dioxide - SiO2 SiO2 = silica = glass ==> dielectric
-excellent I barrier, allows EF
-good chemical resistance - passivation
-step levelling & mechanical protection
-usually layered in combination with SiON & before Si3N4
-not totally impervious=== Si3N4
-exists in deeper layers too - MOS gates

19. SiO2 Wet Etching HF with or without ammonium flouride, NH4F.
addition of NH4F =buffered HF(BHF) = buffered oxide etch (BOE).
HF:NH4HF:H2O (BOE)=>1:5:5
--> 20 Å/s both SiO2 & metals are etched but Si3N4 & Si are spared---S---
NH4F addition controls pH value and replenishes the depletion of the fluoride ions, thus maintaining stable etch rate.
Types :
- 49% HF - fast removal of oxide, poor photoresist adhesion
- BHF - medium removal of oxide, with photoresist mask
- Dilute HF - removal of native oxide, cleanning, surface treatments

20. Aqueous / Non- aqueous Reactions
SiO2 + 6HF -> H2SiF6 + 2H2O
SiO2 + 3HF2- + H+ -> SiF H2O
Fluorosilicic/Hexafluorosilicic acid results
SiO2 + 4HF -> SiF4 + 2H20
Tetrafluorosilane/Silicon tetrafluoride results
SiO2 + 4HF + 2NH4F -> (NH4)2SiF6 + 2H2O

21. Types of SiO2 & etching Thermal SiO2 BOE (7:1) 1,000 Å/min
1:1HF:HCl 23,000 Å/min
49% HF 18,000 Å/min
72 °C Å/min
90 °C Å/min
CVD SiO2 (LTO) BOE (7:1) 3,300 Å/min
1:1 HF:HCl 6,170 Å/min
49% HF
P doped SiO2 BOE (7:1) Å/min
(spin-on dopant) 1:1 HF:HCl 25,000 Å/min
(Photoresist adhesion problems) 49% HF
Boron doped SiO2 BOE (7:1) Å/min
(spin-on dopant) 1:1 HF:HCl
Phosphosilicate Glass (PSG) BOE (7:1) 10,000 Å/min
1:1 HF:HCl 11,330 Å/min
49% HF 28,000 Å/min

22. All are SiO2 !!!??? Production methods : Thermal oxides CVD oxides
Pyrolytically generated oxides
Sputter oxides
Spin-on dopants
Produce bonds of varying strengths / structures ==>need for differing methods

23. SiO2 Wet Etching conducting lines? usually Al but recently Cu
Basic chemistry -:-: aqueous acids etch metal
--> Al etched within few s
Solution : HF/Glycerin mixtures – special applications
A mixture of 5 parts BOE and 3 parts Glycerin works well. Etch rate is unaffected by the Glycerin.

24. Other routes… BOE 1:5:5 HF:NH4HF:H2O 20 A/s
3:2:60 HF:HNO3:H A/sec at Troom
BHF 1:10, 1:100, 1:20 HF:NH4F(sat)
Secco etch 2:1 HF:1.5M K2Cr2O7
5:1 NH4.HF:NaF/L (in grams)
1g:1ml:10ml:10ml NH4F:HF:H2O:glycerin
HF – hot
1:1 1:15, 1:100 HF:H2O
5:43, 1:6 HF:NH4F(40%)
NaCO3 100 C microns/h
5% NaOH 100 C mm/h
5% HCl 95 C microns/day

25. Al Interconnects ~1m thick x 2-25m wide Because -good conductivity
-easy, vacuum thin film deposition
-good adhesion to SiO2
-excellent mechanical bond to Si
-low-R, non-rectifying contacts with p- & hi-doped n-Si
-applied&patterned in single deposit&etch process

26. Al Wet Etching =>metal - easily etched by most acids/bases<=
Aluminum Etchant Type A(Transene Co., Inc.) = phosphoric acid + acetic acid + nitric acid. Al/1%Si leaves behind a silicon residue unless the aluminum etch is heated to 500C.
HCl & ~30% each, between Tr - 500C. Concentration and temperature are not critical, since oxides and silicon are not attacked even for longer etching times.

27. Al Wet Etching- std H3PO4 : H2O : CH3COOH : HNO3 @ 16:2:1:1
==>PAN Etch; C; C
NaOH : 1:1 may be used at 250C but higher T
H3PO4 --- must be heated to 1200C
initial etching delayed by natural aluminium hydroxide layer, up to 5 nm thick - all procedures
Reaction initiation and extinction marked by start and end of gas generation
Post-treatment- sufficient to rinse well in DIW and IPA / acetone, possibly under ultrasound, and blow dry with filtered compressed air (CDA / N2) or warm air under hot-air drier.

28. …these will do too.. Concen. Etchants Rate (A/sec) Temp./Other
1:1 H2O:HF
1:1:1 HCl:HNO3:H2O
dilute or Conc. HCl
H3PO4:HNO3:HAc
19:1:1:2 H3PO4:HAc:HNO3:H2O 40
3:1:3:1 H3PO4:HAc:HNO3:H2O RT @ 40 C < min/micron
4:4:1:1 H3PO4:HAc:HNO3:H2O 5.6
15:0:1:1-4 H3PO4:HAc:HNO3:H2O C
8:1:1 H3PO4:H2O2:H2O @ 35 C
3:1:5 H3PO4:H2O:glycerin
69:131 HClO4:HAc
4:1:5 HCl:FeCle:H2O
FeCl3:H2O F
10% K3Fe(CN)
KOH:K3Fe(CN)6:K2B4O7.4H2O
2:3:12 KMnO4:NaOH:H2O
1:1:3 NH4OH:H2O2:H2O
20% NH4SO4
dilute or
concetrated NaOH
8-10% KOH
CCl boiling
10% Br2:MeOH warm

29. Si Substrate Easily doped - p / n Well characterised Mature technology
Cheap resources -Sarawak best

30. Si Wet Etching Unlike previous materials Usually for structures-MEMS
Depends on Miller index

31. WOW!

32. Si Wet Etching Isotropic Anisotropic HF:HNO3:CH3COOH:H20 HF HF:NH4F
KOH
EDP (Ethylenediamine Pyrocatechol)
CsOH
NaOH
N2H4-H20 (Hydrazine)

33. Si Wet Etching

34. …and the etchant is… For Silicon
KOH = Anisotropic Etching - potassium hydroxide
HF : HNO3 : 2:2:1
HNO3: HF : Acetic 5:3:3
NaOH in Water ---used for dissolving the Si die from the package to allow inspection of eutectic dieattach; 16 T~boiling
For Polysilicon
HNO3 : Water : 50:20:1 - remove oxide first; C
HNO3 : 3:1- remove oxide first; high etch rate: 4.2 micron/min

35. Si Wet Etching
Heated KOH solutions -preferential etching of Si along crystal planes.
Etch rate depends on the doping and crystal orientation of the Si and the type of KOH solution :typically ~1micron/minute.
Potassium (K+) is an extremely fast-diffusing alkali metal ion, and a lifetime killer for MOS devices
1:1:1 H2O:H2O2:HCl and 5:1:1 H2O:H2O2:HCl solutions used for decontamination of wafers & labware following KOH etching
KOH solutions are caustic. hazard classifications : Corrosive, air/water reactive . If using Isopropyl Alcohol in your KOH solution = solvent and Flammable .

36. Additional information
Si3N4 = perfect masking material for KOH etch solution. - -etch rate for Si3N4 ~0.
SiO2 as a masking layer with a KOH solution both T and
concentration should be chosen as low as possible. LTO is not the same as thermal oxide and can be attacked by KOH at a much higher rate. KOH etch rate is about 50 to 55 μm/min at 720 C and KOH concentrations between 10 and 30 wt %. The Si/SiO etch ratio is 1000:1 for 10% KOH at 600 C, at 30% it
drops to 200:1. The relative etch rate of doped silicon to lightly doped silicon decreases for doping concentrations above 1E19 and at 1E20 the relative etch rate is 1/100 for 10% concentration. (on (100) wafer the angle is 50.6｡)

37. Some chemistry… HF + HNO3 + H3COOH = HNA
-nearly isotropic etching of Si
Si + HNO3 + 6HF --> H2SiF6 + HNO2 + H2O + H2
Etching redox reaction followed by dissolution of the
oxide by an acid (HF) that acts as a complexing agent.
- Points on the Si surface randomly become oxidation or reduction sites - act like localized electrochemical cells, sustaining corrosion currents of ~100 A/cm2 (relatively large).
Each point on the surface becomes both an anode and cathode site over time. If the time spent on each is the same, the etching will be uniform; otherwise selective etching will occur.
Without HAc…
3Si + 4HNO HF H2 SiF6 + 4NO + 8H20

38. …more chemistry. Si + 2OH- + 2H2O --> Si(OH)22- + 2H2
A very complex chemistry - still debated

39. Points to ponder most aqueous acids attack metals - Al
IC layers are usually Si3N4 followed by SiON or SiO2 OR a combination of latter two - low S
Undercut due to isotropic nature
Low aspect ratio (height/width ratio)
Residues / contaminants etc..

40. BUT for FA Si etching = substrate removal
=> Underside approach = backside FA as opposed to frontside FA

41. CHIP surface cleaning
Wet etching leaves residues / contaminants / impurities
==> chip needs cleaning
==>usually after each run of wet etching
==>standard procedures use DIW, Alcohol, CDA, Ultrasonics etc..

42. Unwanted stuff
i) residues of moulding materials or protective coverings such as silicone or imide, possibly also adhesive;
ii) corrosive materials and corrosion products already present in the part;
iii) salts, electrolytic residues, moisture, which, for example, remain after inadequate rinsing and drying following the opening of plastic packages;
iv) oily or fatty layers, high-boiling organic solvents;
v) dust particles from the air, fingerprints, etc.

43. TO remove them DIW wash - generous IPA / Acetone - dip CDA / dry N2
**primary purpose ==> preparatory step for subsequent analysis**

44. When deprocessing, it is important to remove each layer totally before proceeding to the next layer. The SEM photo is an IC which has been etched for 15 minutes in wet nitride etch at C. That etch time is about 2 minutes longer than necessary to remove 1 micron of nitride passivation. The over etch time assures that no nitride remains. Residual plasma nitride would act as a mask preventing uniform removal of underlaying oxide as shown in the next SEI

45. This SEM image is the same IC wafer
This SEM image is the same IC wafer. After the nitride passivation is removed, interlayer dielectric layers are removed by etching in 49% HF at room temperature for about 7 seconds.The HF removes the oxide portion of passivation and most of the interlayer oxide. The gate polysilicon, metal 1, and metal 2 are all exposed. The most critical part of this process is the timing of the HF dip. There is little tolerance between just exposing the under layers and causing the second layer of metal to be undermined and float away. This problem is best handled by breaking up the etch time into 2-3 second segments. If the intent is to remove metal 2 leaving metal 1 intact, then metal etch should be used directly after wet nitride etch.

46. This SEM image is after 12 minutes in nitride etch at 120-130C
This SEM image is after 12 minutes in nitride etch at C. The passivation removed is about 0.9 microns of plasma nitride over about 0.1 micron of deposited SiO 2. The goal of this step is to expose metal 2 while leaving metal 1 protected by interlayer dielectric.

47. This SEM image shows the same area after metal 2 was removed by a 5 second etch in freshly mixed 1:1 combination of 98% H2SO4 and 30% H2O2 = pirahna etch, self heats upon mixing and is very aggressive. It attacks organics and most metals.Pirahna etch may not be suitable for deprocessing a packaged die because the package material will be attacked. Note that ridges in the dielectric define the path of removed metal lines. This information should be documented before removing dielectrics with an HF etch

48. REFERENCES INTEGRATED CIRCUITS - K.R.BOTKAR (KHANNA PUBLISHERS)
WET ETCHING RECIPES - SEMICON FAREAST.COM (WEB)
WET ETCHING - A.G. ANDREOU and J. WANG (WEB)
-BRIGHAM YOUNG UNIVERSITY (WEB)