1. C H A P T E R 13 Output Stages and Power Amplifiers Power Amplifiers Power ≈ 1W Small signal model 不適用

2. 2 A. I I C I > I C, θ=360 B. I C = 0, θ=180 Figure 13.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d) class C amplifier stages.

3. 3 A B 類. θ > 180C. θ < 180, 通訊 Figure 13.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d) class C amplifier stages.

4. 4 定電流 I ≥ |-Vcc +Vc E2sat | / R L (13.5)

5. 5 Figure 13.3 Transfer characteristic of the emitter follower in Fig. 14.2. This linear characteristic is obtained by neglecting the change in v BE1 with i L. The maximum positive output is determined by the saturation of Q 1. In the negative direction, the limit of the linear region is determined either by Q 1 turning off or by Q 2 saturating, depending on the values of I and R L. V 0(max ) V 0(min ) Q 1 off

6. 6 Figure 13.4 Maximum signal waveforms in the class A output stage of Fig. 14.2 under the condition I = V CC /R L or, equivalently, R L = V CC /I. P D(max ) = i c 1 =I P D = i c 1 * V CE1 (14.7) η ≡ P L / P S (14.8) 平均 P L = V 0 2 /2R L P S = 2 * V CC * I η max ≡ 25%

7. 7 Push - pull * 無 bias I Figure 13.5 A class B output stage.

8. 8 Figure 13.6 Transfer characteristic for the class B output stage in Fig. 13.5. QNQN QpQp dead band

9. 9 Figure 13.7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion. (14.12) P L = V 0 2 /2R L average current = V 0 /πR L (14.13)P S + = P S- = (V 0 /πR L ) * V CC η max = π/4 = 78.5 % (14.16)

10. 10 Figure 13.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid. P L – P S = P D (14) - (12) ----> (19) P D = 2V 0 V CC /πR L – V 0 2 /2R L әP D / әV 0 = 0 V 0 | P D max = 2V CC /π P D max = 2V CC 2 /π 2 R L

11. 11 Figure 13.9 Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion. A 0 (V I -V 0 ) V0V0 V I > V 0 + 0.7/A 0  Q N 即 ON

12. Microelectronic Circuits, International Sixth Edition Figure 13.10 Class B output stage operated with a single power supply.

13. 13 Figure 13.11 Class AB output stage. A bias voltage V BB is applied between the bases of Q N and Q P, giving rise to a bias current I Q given by Eq. (14.23). Thus, for small v I, both transistors conduct and crossover distortion is almost completely eliminated. V BB bias Static ： i N = i P = I Q V BB ≈ 2V BE(ON) V 0 = V I + V BB /2 –V BEN (14.24) (14.26) i N * i P = I Q 2 V I > 0, 且很小  i N ↑, i P ↓ 且很大  i N ↑ ↑, i P = 0

14. Microelectronic Circuits, International Sixth Edition Figure 13.12 Transfer characteristic of the class AB stage in Fig. 13.11.

15. 15 Figure 13.13 Determining the small-signal output resistance of the class AB circuit of Fig. 13.11. (14.28) R out = r en // r ep = (14.31) = V T / ( i P + i N )

16. 16 Figure 13.14 A class AB output stage utilizing diodes for biasing. If the junction area of the output devices, Q N and Q P, is n times that of the biasing devices D 1 and D 2, and a quiescent current I Q = nI BIAS flows in the output devices. thermal runaway : temp ↑, i c N ↑ ↑  temp ↑ *temp ↑  I D(ON) 不變  V D(ON) ↓  V BB ↓  i c ↓  temp ↓

17. 17 Figure 13.15 A class AB output stage utilizing a V BE multiplier for biasing. V BE1 (1 + R 2 /R 1 ) = V BE1

18. 18 Figure 13.16 A discrete-circuit class AB output stage with a potentiometer used in the V BE multiplier. The potentiometer is adjusted to yield the desired value of quiescent current in Q N and Q P. I R = V BE1 / R 1 (14.32) V BE1 I R I C1 I bN V 0 很大, I bN 不小 I C1 ↓  V BE1 小一點點  V BB 幾乎不變

19. Microelectronic Circuits, International Sixth Edition

20. Figure 13.18 An alternative CMOS output stage utilizing a pair of complementary MOSFETs connected in the common- source configuration. The driving circuit is not shown.

21. Microelectronic Circuits, International Sixth Edition Figure 13.19

22. Microelectronic Circuits, International Sixth Edition

23. Figure 13.21

24. Microelectronic Circuits, International Sixth Edition Figure 13.22

25. Microelectronic Circuits, International Sixth Edition

26. 26 Figure 13.24 Maximum allowable power dissipation versus ambient temperature for a BJT operated in free air. This is known as a “power-derating” curve. P D T A T j - T A = θ jA * P D (14.36) (14.38) P D max = (T j max - T A ) / θ jA

27. Microelectronic Circuits, International Sixth Edition Figure 13.25 The popular TO3 package for power transistors. The case is metal with a diameter of about 2.2 cm; the outside dimension of the “seating plane” is about 4 cm. The seating plane has two holes for screws to bolt it to a heat sink. The collector is electrically connected to the case. Therefore an electrically insulating but thermally conducting spacer is used between the transistor case and the “heat sink.”

28. 28 Figure 13.26 Electrical analog of the thermal conduction process when a heat sink is utilized. case sink Ө jA =Ө jC +Ө CA

29. 29 Figure 13.27 Maximum allowable power dissipation versus transistor-case temperature. P Dmax = Tjmax-Tc / Ө jc j c ( 廠商 )

30. 30 Figure 13.28 Thermal equivalent circuit for Example 14.5. Heat 全沒了

31. 31 Figure 13.29 Safe operating area (SOA) of a BJT. i0i0 V0V0 Melting wire (P Dmax ) Emitter crowding (hot spot) V BE

32. 32 Figure 13.30 A class AB output stage with an input buffer. In addition to providing a high input resistance, the buffer transistors Q 1 and Q 2 bias the output transistors Q 3 and Q 4. Bias V BB 負回授. *Ri

33. 33 Figure 13.31 The Darlington configuration.

34. Microelectronic Circuits, International Sixth Edition Figure 13.32 The compound-pnp configuration.

35. 35 Figure 13.33 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained using a V BE multiplier. Darlington compound

36. 36 Figure 13.34 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while v O is positive. 平時 Q5 off i L ↑↑( 及 ie 1 很大 ) →V be5 ↑(Q 5 ON) →i b1 ↓→ie 1 ↓ ib1 ics ie1

37. 37 Figure 13.35 Thermal-shutdown circuit. Power Amp. Vcs Sink IQ ( 並聯 ) 導熱 平時 Q 2 off temp↑→V Z1 ↑→Ie 1 ↑→Vb 2 ↑ →Q 2 ON

38. 38 Figure 13.36 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.) (14.45) V0=VS/2 Q3.Q4:diff. amp. Q1.Q2:Vi buffer Q5.Q6:active load I3I3 負回授 I4 為負 F.B. V0↑→i4↑ →ic4↑ →ic12↑( I3 固定 ) →ib7↓ →V0↓ 主 O/P i/P I3I3

39. 39 Figure 13.37 Small-signal analysis of the circuit in Fig. 14.30. The circled numbers indicate the order of the analysis steps. 6 + 9 = 10 Vi/R 3 +V0/r 2 +Vi/R 3 =0 10 14 Av=-50

40. Microelectronic Circuits, International Sixth Edition Figure 13.38 Power dissipation (P D ) versus output power (P L ) for the LM380 with R L = 8V. (Courtesy National Semiconductor Corporation.)

41. 41 Figure 13.39 Structure of a power op amp. The circuit consists of an op amp followed by a class AB buffer similar to that discussed in Section 14.7.1. The output current capability of the buffer, consisting of Q 1, Q 2, Q 3, and Q 4, is further boosted by Q 5 and Q 6. Booster 增幅 Q 3 ON, Ic 3 ↑, →V Q5 ↓ →Q 5 ON I C5 ↑↑

42. 42 Figure 13.40 The bridge amplifier configuration. V+ V- A1 A2 為 power OP.amp

43. 43 Figure 13.41 Double-diffused vertical MOS transistor (DMOS). *power MOSFET N+P+N-N+ 壓降 300u↑ V D (500V) S P N+ VGVG S VDVD

44. 44 Figure 14.42 Typical i D – v GS characteristic for a power MOSFET. *V-groove MOS (14.46) i D ∝ C 0 *u*(W/L)(V GS -Vt)² (14.47) i D ∝ Usat(V GS -Vt) 定 ↓ [(V G s-Vt) /L] * u

45. 45 Figure 13.43 The i D – v GS characteristic curve of a power MOS transistor (IRF 630, Siliconix) at case temperatures of –55  C, +25  C, and +125  C. (Courtesy Siliconix Inc.) *Power MOS 無 thermal runaway *Vgs 小時, temp ↑ →Vt↓ →id↑ *Vgs 大時, temp ↑ → u ↓→ id ↓ ic V BE

46. 46 Figure 13.44 A class AB amplifier with MOS output transistors and BJT drivers. Resistor R 3 is adjusted to provide temperature compensation while R 1 is adjusted to yield the desired value of quiescent current in the output transistors. Resistors R G are used to suppress parasitic oscillations at high frequencies. Typically, R G = 100 . Power MOS Switching faster