1. Synchronization Hierarchy & Some Ways to Fool Your Synchronizer University of Tehran VLSI Course By: Mahshid Sedghy

2. A Quick Overview Introduction Synchronization Hierarchy Mesochronous synchronizers A correct Two Flop Synchronizer Avoiding the Synchronizer The interesting synchronizers

3. Introduction Transferring data between mutually asynchronous clock domains requires safe synchronization Some synchronization Methods used For each level of synchronization hierarchy

4. Synchronization Hierarchy TypeFrequencyPhase SynchronousSame MesochronousSameConstant PlesiochronousSmall DifferenceSlowly Variation PeriodicDifferentPeriodic Variation AsynchronousN/AArbitrary

5. A correct Two Flop synchronizer Synchronization reliability is typically expressed in terms of Mean Time Between Failures: A Push synchronizer

6. Push Synchronizer logic and protocol FSM

7. Three synchronization scenarios a. The rising edge of R is sampled high. b. The rising edge of R is sampled low. c. The first flop goes metastable. Three possible outcomes may happen:

8. Avoiding the synchronizer The most common synchronization error The rate of entering metastablity is Tw*fD*fC Static timing analysis would generate setup and hold violation warnings for every signal that cross domain boundaries The error can be detected by clock domain crossing analysis The crossing lists are used as “false-path” specification

9. The Interesting Synchronizers 1. One Flop Synchronizer The problem comes about when there’s a clock-data conflict Is legal when T-d assures the required MTBF

10. The Interesting Synchronizers 2. Greedy path Synchronizer

11. The Interesting Synchronizers 3. Global Reset Synchronizer

12. The Interesting Synchronizers 4. Async Clear Synchronizer Asynchronous clear Synchronized-trail clear

13. The Interesting Synchronizers 5. Pulse Synchronizer

14. Conclusions As long as there are no foolproof algorithms and tools to validate synchronizers, the rules to safe design should be closely watched Optimizations that may impede future design reuse should be avoided. Global signals that span multiple domains, such as reset and clocks, should be examined carefully.

15. References Fourteen ways to Fool Your Synchronizer By :Ran Ginosar VLSI Systems Resaerch Center,Technion Israel Institue of Technology February 2003 Synchronizer Design William J. Dally Computer Systems Laboratory, Stanford University November 11, 1998