Presentation is loading. Please wait.

Presentation is loading. Please wait.

PicoBlaze & MicroBlaze

Similar presentations

Presentation on theme: "PicoBlaze & MicroBlaze"— Presentation transcript:

1 PicoBlaze & MicroBlaze
Ernest Jamro Dep. Of Electronics AGH – University of Science and Technology

2 MicroBlaze 32 bit soft-processor 32 bit instructions 32 registers
Independent data and instruction buses Different bus standards: - PLB (Processor Local Bus) - AXI (Advanced eXtensible Interface) - LMB (Local Memory Bus) - FSL (Fast Simplex Link)

3 MicroBlaze Block Diagram

4 Different Bus Configurations
LMB: AXI / PLB Complexity simply complex Local/glonal local global # Master 1 >=1

5 MB bus configurations: only LMB This configuration cannot communicat with external modules, thus should not be employed

6 LMB: Instructions, PLB:Data

7 EDK Print Screen

8 Instructions:LMB; Data: PLB + LMB MB employs LMB for instructions and memory access and PLB/AXI for peripheral module access

9 Only one PLB/AXI bus

10 Two PLB/AXI buses Warning: plb_ddr memory cannot be written (how to initialise instruction memory)

11 Two PLBs, single memory

12 Without Data Cache Manual (in C program) handling of data memory transfer

13 Example (6) The MB is booted from BRAM

14 Fast Simplex Link (FSL)
32-bit single direction bus – one master one slave

15 Registers R0-R31 32x32-bit –general purpose registers R0- always equal to 0 PC – Program counter – initial value = 0 MSR (Machine State Register)

16 MSR

17 Instruction Format Typu A Instruction Typu B instruction
Example: instruction ADD

18 Example of Instructions


20 Pipeline Architecture
Delay Slot Instructions

21 (Hard)Procesor (e.g. PowerPC in Virtex 2Pro)
Implemented directly in silicon (ASIC technology) Employs ASIC technology (not FPGA technology) so this silicon area cannot be reused for other purposes Parameters are defined (ASIC) and cannot be changed Is relatively fast and consumes relatively small silicon area and power

22 Soft-procesor (e.g. MicroBlaze)
Employs standard FPGA logic resources thus the logic resources can be freed when not required Parameters can be freely defined by a user In comparison to the hard-processor is slower, consumes more silicon area and power

23 MicroBlaze parameters
Different types of buses (PLB/AXI, LMB) (Implement or not) cache memory, define its size Barrel-Shifter fast multiplier: define the bit-width of the multiplier: 32-bit, 64-bit divider debugger (and its parameters) Floating-point unit (and its parameters) MMU – Memory Management Unit

24 EDK - Ports

25 EDK Addresses

26 Adding IP-Cores

27 IP-Core Options

28 Microprocessor Hardware Specification

29 8-bit soft-processor PicoBlaze
• Optimized for Xilinx Spartan-3 architecture—just 96 slices (0.3% of an XC3S5000 device) and 0.5 to 1 block RAM 16 byte-wide general-purpose data registers • 1K instructions of programmable on-chip program store, automatically loaded during FPGA configuration • Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags • 64-byte internal scratchpad RAM • 256 input and 256 output ports for easy expansion and enhancement • Automatic 31-location CALL/RETURN stack • Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-II Pro FPGA • Fast interrupt response; worst-case 5 clock cycles • Support in Spartan-6, and Virtex-6 FPGA architectures • Assembler, instruction-set simulator support

30 Block diagram

31 Example, external multiplier

32 PicoBlaze, in VHDL processor: kcpsm
port map( address => address_signal, instruction => instruction_signal, port_id => port_id_signal, write_strobe => write_strobe_signal, out_port => out_port_signal, read_strobe => read_strobe_signal, in_port => in_port_signal, interrupt => interrupt_signal, reset => reset_signal, clk => clk_signal);

33 PB, assembler

34 PB, data moving

35 MicroBlaze – cache memory
Small cache memory is much quicker than external memory For the MB it is better to use internal BRAM memory (in the case when data moving is easily determined) than cache as BRAM as quick as cache memory but consumes less recourses

36 cache block structure This structure is for tutorial-pupose only (not used in real applications)

37 Real Application

38 The End

39 Uproszczony przykład działania
Linie adresowe: a30-a31 – ignorowane – dane są 4 bajtowe a24-a29 – linie adresowe pamięci tag i danych (instrukcji) a0-a23 – linie adresowe zapisywane w pamięci tag i wykorzystywane podczas porównywania Pamięć Tag CacheL. DanaTag Cache adr 0 0x00 0x0000 1 0x00 0x0004 2 0x00 0x0008 3 0x03 0x030C 4 0x03 0x0310 5 0x05 0x0514 6 0x06 0x0618 7 0x07 0x071C ...

40 LMB (Local Memory Bus) Sygnały

41 LMB (odczyt i zapis)

42 LMB szybki odczyt

Download ppt "PicoBlaze & MicroBlaze"

Similar presentations

Ads by Google