1. Chapter 6 Computer Architecture

2. Computer Components: Top Level View

3. Instruction Cycle
Two steps:
Fetch
Execute

4. Program Counter (PC) holds address of next instruction to fetch
Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs required actions

5. Execute Cycle Processor-memory Processor I/O Data processing Control
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above

6. Example of Program Execution

7. Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error

8. Transfer of Control via Interrupts

9. All the units must be connected
Connecting
All the units must be connected
Different type of connection for different type of unit
Memory
Input/Output
CPU

10. Computer Modules

11. A communication pathway connecting two or more devices
What is a Bus?
A communication pathway connecting two or more devices
Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels

12. Width is a key determinant of performance
Data Bus
Carries data
Remember that there is no difference between “data” and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit

13. Identify the source or destination of data
Address bus
Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
Bus width determines maximum memory capacity of system
e.g has 16 bit address bus giving 64k address space

14. Control and timing information
Control Bus
Control and timing information
Memory read/write signal
Interrupt request
Clock signals

15. Bus Interconnection Scheme

16. Physical Realization of Bus Architecture

17. Cache Memory

18. Memory Hierarchy - Diagram

19. Access Methods (1) Sequential Direct
Start at the beginning and read through in order
Access time depends on location of data and previous location
e.g. tape
Direct
Individual blocks have unique address
Access is by jumping to vicinity plus sequential search
Access time depends on location and previous location
e.g. disk

20. Access Methods (2) Random Associative
Individual addresses identify locations exactly
Access time is independent of location or previous access
e.g. RAM
Associative
Data is located by a comparison with contents of a portion of the store
e.g. cache

21. Physical Types
Semiconductor
RAM
Magnetic
Disk & Tape
Optical

22. Hierarchy List
Registers
L1 Cache
L2 Cache
Main memory
Disk
Optical
Tape

23. Cache
Small amount of fast memory
Sits between normal main memory and CPU
May be located on CPU chip or module

24. Cache/Main Memory Structure

25. Cache operation – overview
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast)
If not present, read required block from main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block of main memory is in each cache slot

26. Typical Cache Organization

27. Comparison of Cache Sizes
Comparison of Cache Sizes
Processor
Type
Year of Introduction
L1 cachea
L2 cache
L3 cache
IBM 360/85
Mainframe
1968
16 to 32 KB —
PDP-11/70
Minicomputer
1975
1 KB
VAX 11/780
1978
16 KB
IBM 3033
64 KB
IBM 3090
1985
128 to 256 KB
Intel 80486 PC
1989
8 KB
Pentium
1993
8 KB/8 KB
256 to 512 KB
PowerPC 601
32 KB
PowerPC 620
1996
32 KB/32 KB
PowerPC G4
PC/server
1999
256 KB to 1 MB
2 MB
IBM S/390 G4
1997
256 KB
IBM S/390 G6
8 MB
Pentium 4
2000
IBM SP
High-end server/ supercomputer
64 KB/32 KB
CRAY MTAb
Supercomputer
Itanium
2001
16 KB/16 KB
96 KB
4 MB
SGI Origin 2001
High-end server
Itanium 2
2002
6 MB
IBM POWER5
2003
1.9 MB
36 MB
CRAY XD-1
2004
64 KB/64 KB
1MB
a Two values seperated by a slash refer to instruction and data caches
b Both caches are instruction only; no data caches

28. Mapping Function Cache of 64kByte Cache block of 4 bytes
i.e. cache is 16k (214) lines of 4 bytes
16MBytes main memory
24 bit address
(224=16M)

29. Each block of main memory maps to only one cache line
Direct Mapping
Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place

30. Direct Mapping Example

31. Associative Mapping
A main memory block can load into any line of cache
Cache searching gets expensive

32. Associative Mapping Example

33. Set Associative Mapping
Cache is divided into a number of sets
Each set contains a number of lines
A given block maps to any line in a given set
e.g. Block B can be in any line of set i
e.g. 2 lines per set
2 way associative mapping
A given block can be in one of 2 lines in only one set

34. Replacement Algorithms (1) Direct mapping
No choice
Each block only maps to one line
Replace that line

35. Replacement Algorithms Associative & Set Associative
Least Recently used (LRU)
e.g. in 2 way set associative
Which of the 2 block is lru?
First in first out (FIFO)
replace block that has been in cache longest
Least frequently used
replace block which has had fewest hits
Random

36. Write Policy
Write through
Write back

37. Write through
All writes go to main memory as well as cache
Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date
Slows down writes

38. Updates initially made in cache only
Write back
Updates initially made in cache only
Update bit for cache slot is set when update occurs
If block is to be replaced, write to main memory only if update bit is set