1. 1 Pertemuan 3 Karakteristik Logik Gerbang MOSFET Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2. 2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan karakteristik logik gerbang MOSFET.

3. 3 Ideal Switch a b a. 1 b. 1 1 + f = a + b Hubungan paralel: x y a = 0 x y a = 1 buka tutup ab 1 a. 1(a. 1). b g = a. b Hubungan seri: Assert-high

4. 4 Ideal Switch ab 1 a. 1(a. 1). b g = a. b Hubungan seri: Assert-low x y a = 1 x y a = 0 buka tutup Gerbang NOT: f = a. 1 + a. 0 = a a a a. 1 a. 0 1 + 0 a 1 0 f(x) = a. 1 + a. 0 Mux

5. 5 MOSFET Switch Source Drain Source Gate nFET pFET Simbol + - + - V DD V SS Power supply V DD > 0 V V SS < 0 V Ke chip Dual power supply voltages + - V DD Rangkaian CMOS Single voltage power supply 0 V DD Logik 1 Logik 0 Tak tentu

6. 6 x y = ? a = 0 x y = x a = 1 buka tutup nFET x y = ? a = 1 x y = x a = 0 buka tutup pFET MOSFET Switch

7. 7 nFET VAVA Gate Source Drain + - V GSn Mn Ke V DD VAVA V Tn V DD A = 1 Mn ON A = 0 Mn OFF VAVA Gate Source Drain + - V SGp Mp V DD VAVA (VDD - |V Tn |) V DD A = 1 Mp OFF A = 0 Mp ON pFET Ke ground Threshold voltage MOSFET Switch

8. 8 in out V DD V x = 0 V + - + - V y = 0 V in out V DD V x = V DD + - + - V y = V DD - V Tn + - V Tn in out V x = 0 V + - + - V y = |V Tp | |V Tp | - + Pass Characteristics nFET in out V x = V DD + - + - V y = V DD pFET MOSFET Switch

9. 9 Gerbang Logik CMOS Control block a b c inputs 1 0 V SS SWn SWp V DD f (a, b, c) output Control block a b c inputs 1 0 V SS buka tutup V DD f = 1 Control block a b c inputs 1 0 V SS tutup buka V DD f = 0

10. 10 Gerbang Logik CMOS Gerbang NOT Ke V DD Mp Mn pFET nFET x Ke V SS Pasangan complement CMOS Ke V DD Mp ON Mn OFF X = 0 Ke V SS Ke V DD Mp OFF Mn ON X = 1 Ke V SS x x x 0 1 1 0 Mp Mn x V DD x

11. 11 Gerbang Logik CMOS Gerbang NOR A B F 0 0 1 0 1 0 1 0 0 1 1 0 A B F 01230123 0101 ABAB 10001000 Mux F = A + B Mpx Mpy Mnx Mny A B 1. A. B 0. B 0. A F = A + B V DD

12. 12 Gerbang Logik CMOS Gerbang NAND 01230123 0101 ABAB 11101110 Mux F = A. B Mpx Mnx Mny A B Mpy 1. A F = A. B V DD 1. B 0. A. B A B F 0 0 1 0 1 1 1 0 1 1 1 0 A B F

13. 13 Gerbang Logik CMOS N Fan-out N Fan-in M M

14. 14 Gerbang Logik CMOS Gerbang Complex A B V DD 1. A C 1. B. C F = A. 1 + (B. C). 1 A B C B C A F F F = A. (B + C) = A + (B + C) = [A + (B. C)]. 1 = A. 1 + (B. C). 1 A B C 0. [A. (B + C)] 0. (B + C) F = 0 jika A = 1 AND (B+C ) = 1 0. [A. (B + C)] V DD B C A B A F C

15. 15 Clock dan Aliran Data 1 1 0T 2T   time Blok 1 Blok 2 Blok 3    System clock Block level system timing diagram

16. 16 RESUME Ideal Switch: assert high, assert low. MOSFET Switch: nFET, pFET. Gerbang logic CMOS. Clock dan aliran data.