1. 1 Sequential Circuits –Digital circuits that use memory elements as part of their operation –Characterized by feedback path –Outputs depend not only on its current inputs but also on the past sequence of inputs, possibly arbitrarily far back in time Examples –Counters –Parallel-to-Serial conversion of byte data

2. 2 Sequential Circuits State of Circuit –Binary information stored in the memory elements determines the “state” of the circuit –Output and next state is determined by input signals and current state of circuit

3. 3 Sequential Circuits 2 Major Types of Circuits Asynchronous –Inputs may change at any time –Complicated and maybe unstable because of feedback Synchronous –Input change is only effected at certain times determined by a master clock (pulse or edge detection) or master-slave operation

4. 4 Asynchronous Sequential Circuits Latch Temporary storage device that has two stable states Normally has two inputs Two complementary outputs available: Q and Q’ When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state A latch serves as a memory element which is able to retain the information stored in it

5. 5 S-R (Set-Reset) Latch InputOutput SRQ t+1 00QtQt 010 101 11Invalid NOR gate based

6. 6 S-R (Set-Reset) Latch Truth table Characteristic Equation Q t+1 = S + R’Q;SR = 0 QSRQ t+1 0000 0010 0101 011Invalid 1001 1010 1101 111

7. 7 S-R (Set-Reset) Latch InputOutput S’S’ R’R’ Q t+1 11QtQt 100 011 00Invalid NAND gate based

8. 8 S-R (Set-Reset) Latch Standard Logic Symbols

9. 9 S-R (Set-Reset) Latch Timing diagram of active-low input latch

10. 10 S-R (Set-Reset) Latch Timing diagram of active-high input latch

11. 11 S-R Latch Apps - Burglar Alarm

12. 12 Synchronous Sequential Circuits Latches –Asynchronous circuits –Outputs are transparent to inputs Gated or Clocked Latches –Synchronous circuits b/c clock or enable input dictates when inputs are latched onto outputs –May still have both transparent and latched operation if inputs change while clock is active Flip Flops –Flip-Flops are synchronous bi-stable devices, known as bi-stable multivibrators –The output of the flip-flop can only change once by the applied inputs upon application of clock input –Edge Triggered or Master Slave

13. 13 S-R Gated Latch –Adds a clock (control) input gated to an S-R latch –S/R inputs are passed on to the latch portion synchronised by the clock pulse –Also called Clocked S-R Latch CK

14. 14 S-R Gated Latch Truth table Characteristic Equation Q t+1 = S + R’Q;SR = 0 QSRQ t+1 0000 0010 0101 011Invalid 1001 1010 1101 111

15. 15 S-R Gated Latch Timing

16. 16 D Gated Latch CK

17. 17 D Gated Latch Truth table Characteristic Equation Q t+1 = D QDQ t+1 000 011 100 111

18. 18 D Gated Latch Apps

19. 19 D Gated Latch Timing

20. 20 Latches - Transparency Problem What’s transparency? –Output follows input instantaneously – tunneling –Behavior depicted in latches The transparency problem –If output is fed back, circuit may become unstable The solution? –Master Slave or Edge Triggered FF

21. 21 Transparency Problem

22. 22 Transparency Problem

23. 23 Master Slave Flip Flop

24. 24 Master Slave Flip Flop

25. 25 S-R Master Slave Flip Flop

26. 26 Master Slave Flip Flops Summary Have two stages – Master and Slave Each stage works in one half of the clock signal Inputs are applied in the first half of the clock signal Outputs do not change until the second half of the clock signal Allows digital circuits to operate in synchronization with a common clock signal Inherently slow throughput Mostly obsolete Better Solution: Edge Triggered flip-flops An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal - faster

27. 27 D Flip-Flop Apps – Registers

28. 28 Edge Triggered J-K Flip Flop

29. 29 Edge Triggered J-K Flip Flop InputOutput CLKJKQ t+1 0XXQtQt 1XXQtQt ↑00QtQt ↑010 ↑101 ↑11 Qt’Qt’ InputOutput CLKJKQ t+1 0XXQtQt 1XXQtQt ↓00QtQt ↓010 ↓101 ↓11 Qt’Qt’

30. 30 T Flip Flop Truth table Characteristic Equation Q t+1 = TQ’ + T’Q QTQ t+1 000 011 101 110

31. 31 T Flip Flop

32. 32 Flip-Flop Operating Characteristics Performance specified by several operating characteristics provided in the data sheets of FF’s The important operating characteristics are: –Propagation Delay –Set-up Time –Hold Time –Maximum Clock frequency –Pulse Width –Power Dissipation

33. 33 Flip Flop Logic Symbols Summary

34. 34 Qt+1 = S + R’Q;SR = 0 Qt+1 = D Qt+1 = JQ’ + K’Q Qt+1 = TQ’ + T’Q Flip Flop Characteristic Equations

35. 35 Flip Flop Excitation Tables QtQt Q t+1 SR 000X 0110 1001 11X0 QtQt JK 000X 011X 10X1 11X0 QtQt D 000 011 100 111 QtQt T 000 011 101 110

36. 36 Flip Flop Usage Guide Type of ApplicationPreferred FF Transfer of data (e.g. shift registers) RS or D Complementation (e.g. binary counters) T Above or any other general application JK