1. Chapter 8 Introduction to Sequential Logic

2. 2 Sequential Circuit A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuit.

3. 3 Sequential Circuit Elements Two basic types: –Latch –Flip-flop The difference is the condition under which the stored bit changes.

4. 4 Sequential Circuit Inputs The LATCH is a sequential circuit with two inputs (SET and RESET). SET – an input that makes the device store a logic 1. RESET – an input that makes the device store a logic 0.

5. 5 Sequential Circuit Outputs Two complementary outputs Outputs are always in opposite logic states.

6. 6 Sequential Circuit Outputs

7. 7 Sequential Circuit States

8. 8 Active HIGH or LOW Inputs Latches can have either active HIGH or active LOW inputs. The output of the LATCH, regardless of the input active level, is still defined as:

9. 9 Active HIGH or LOW Inputs

10. 10 NAND Latch Function Table RESET1001 1 1 0 1 1 No Change1 SET00 Forbidden10 Function

11. 11 Function Table Notation Q t indicates the present state of the Q input. Q t +1 indicates the value of Q after the specified input is applied.

12. 12 NAND Latch Operation Two possible stable states: –SET –RESET Feedback keeps the latch in a stable condition.

13. 13 SRQ t + 1 Function 00QtQt No Change 0101RESET 1010SET 1100Forbidden NOR Latch Function Table

14. 14 NOR Latch Function Table

15. 15 Block Diagram File NAND Latch Gate components are called BOR2: –Bubbled-OR, 2-inputs Inputs are labeled nS and nR. Outputs are labeled Q and nQ. –In Quartus, the n prefix takes the place of the logic inversion bar.

16. 16 Block Diagram File NAND Latch

17. 17 Practical Synthesis of the NAND Latch Quartus II does not synthesize the LATCH exactly as shown in Figure 8.15 on the previous slide. Quartus II analyzes the Boolean equation of the original LATCH and reformats the circuit to fit the target device.

18. 18 Quartus II NAND Latch Equations

19. 19 Quartus II NAND Latch Equations

20. 20 Switch Bounce The condition where the closure of a switch contact results in a mechanical bounce before the final contact is made. In logic circuits, switch bounce causes several pulses when a switch is closed. –Can cause circuit to behave unpredictably.

21. 21 Switch Bounce

22. 22 Switch Debounce Circuit Uses a NAND latch with switch contacts connected to +5 volts. Bounce is ignored since that condition results in inputs of: – A no-change condition

23. 23 Switch Debounce Circuit

24. 24 Gated SR Latch The time when a latch is allowed to change state is regulated. Change of state is regulated by a control signal called ENABLE. Circuit is a NAND latch controlled by steering gates.

25. 25 Gated SR Latch

26. 26 Latch ENABLE Input Used in two principal ways: –As an ON/OFF signal –As a synchronizing signal

27. 27 ENSRQ t+1 Function 100QtQt No change 1010 1 Reset 1101 0 Set 1111 1 Forbidden 0XXQtQt Inhibited Gated SR Latch Function Table

28. 28 Gated D or Transparent Latch A latch whose output follows its data input when its ENABLE input is active. When ENABLE is inactive, the latch stores the data that was present when ENABLE was last active.

29. 29 Gated D or Transparent Latch

30. 30 ENDQ t+1 FunctionComment 0XQtQt No changeStore 1001RESETTransparent 1110SET Gated D Latch Function Table

31. 31 D Latches in Quartus II Can be implemented as a primitive in a Block Diagram file (.bdf). Can be implemented with a behavioral or structural description in a VHDL file.

32. 32 D Latches in Quartus II

33. 33 D Latches in Quartus II

34. 34 VHDL Process Statement PROCESS statement is concurrent. Statements inside the PROCESS are sequential.

35. 35 VHDL – D Latch – 1 -- d_latch_vhdl.vhd -- D latch with active-HIGH level-sensitive enable ENTITY d_latch_vhdl IS PORT( d, ena: IN BIT; q: OUT BIT); END d_latch_vhdl;

36. 36 VHDL – D Latch – 2 ARCHITECTURE a OF d_latch_vhdl IS BEGIN PROCESS ( d, ena) BEGIN IF ( ena = ‘1’) THEN q <= d; END IF; END PROCESS; END a;

37. 37 Instantiating a Latch Primitive Primitive is contained in the Altera library, in a package called maxplus2. Component declaration in maxplus2 package. Unnecessary to declare it in the file used.

38. 38 VHDL – Latch Primitive – 1 -- latch_primitive.vhd -- D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL;

39. 39 VHDL – Latch Primitive – 2 ENTITY latch_primitive IS PORT( d_in, enable: INSTD_LOGIC; q_out: OUTSTD_LOGIC); END latch_primitive;

40. 40 VHDL – Latch Primitive – 3 ARCHITECTURE a OF latch_primitive IS BEGIN -- Instantiate a latch from a QUARTUS II primitive latch_primitive: latch PORT MAP (d => d_in, ena => enable, q => q_out); END a;

41. 41 Multibit Latches in VHDL VHDL can be used to implement latches with multiple D inputs and Q outputs and a common ENABLE line. –Use behavioral description with STD_LOGIC_VECTOR types. –Use primitives – predefined components. –Use component from Library of Parameterized Modules (LPM).

42. 42 VHDL – Latch LPM Component – 1 -- latch4_behavioral.vhd -- D latch with active-HIGH level-sensitive enable -- uses a latch component from the -- Library of Parameterized Modules (LPM) LIBRARY ieee; USE ieee.std_logic_1164.ALL; --required for STD_LOGIC types LIBRARY lpm; USE lpm.lpm_components.ALL; -- Required for LPM components

43. 43 VHDL – Latch LPM Component – 2 ENTITY latch4_lpm IS PORT(d_in: INSTD_LOGIC_VECTOR(3 downto 0); enable: INSTD_LOGIC; q_out: OUTSTD_LOGIC_VECTOR(3 downto 0)); END latch4_lpm;

44. 44 VHDL – Latch LPM Component – 3 ARCHITECTURE a OF latch4_lpm IS BEGIN -- instantiate latch from an LPM component latch4 : lpm_latch GENERIC MAP (LPM_WIDTH => 4) PORT MAP ( data => d_in, gate => enable, q => q_out); END a;

45. 45 VHDL – Latch LPM Component – 4

46. 46 Flip-Flop Definition A gated latch with a clock input. The sequential circuit output changes when its CLOCK input detects an edge. Edge-sensitive instead of level- sensitive.

47. 47 CLOCK Definitions Positive edge: –The transition from logic ‘0’ to logic ‘1’ Negative edge: –The transition from logic ‘1’ to logic ‘0’ Symbol is a triangle on the CLK (clock) input of a flip-flop.

48. 48 CLOCK Definitions

49. 49 CLOCK Definitions

50. 50 CLKDQ t+1 Function ↑001RESET ↑110SET 0XQtQt Inhibited 1XQtQt ↓XQtQt Positive Edge-Triggered D Flip- Flop Function Table

51. 51 Positive-Edge Triggered D Flip- Flop Function Table

52. 52 Edge Detector A circuit that converts that active-edge of a CLOCK input into a brief active- level pulse. Created using gate propagation delays. Can be positive or negative edge.

53. 53 Edge Detector

54. 54 Latch/Flip-Flop Behavior The LATCH transfers data from the data inputs to Q on either a HIGH or LOW voltage level at the ENABLE input. The FLIP-FLOP transfers data from the data inputs to Q on either the POSITIVE (rising), or NEGATIVE (falling) edge of the clock.

55. 55 Latch/Flip-Flop Behavior

56. 56 Latch/Flip-Flop Behavior

57. 57 JK Flip-Flop Two inputs with no illegal input states. With J and K both HIGH, the flip-flop toggles between opposite logic states with each applied clock pulse.

58. 58 JK Flip-Flop

59. 59 CLKJKQ t+1 Function ↓00QtQtNo change ↓0101RESET ↓1010SET ↓11QtQt Toggle 0XXQtQt Inhibited 1XXQtQt ↑XXQtQt Negative Edge-Triggered JK Flip- Flop Function Table

60. 60 Negative Edge-Triggered JK Flip- Flop Function Table

61. 61 Toggle Applications Used to divide an input frequency in half. By cascading toggling flip-flops, a counter is created.

62. 62 Toggle Applications

63. 63 Toggle Applications

64. 64 Synchronous Versus Asynchronous Circuits Synchronous circuits have sequential elements whose outputs change at the same time. Asynchronous circuits have sequential elements whose outputs change at different times.

65. 65 Synchronous Versus Asynchronous Circuits

66. 66 Synchronous Versus Asynchronous Circuits

67. 67 Disadvantages of Asynchronous Circuits Difficult to analyze operations. Intermediate states that are not part of the desired design may be generated.

68. 68 Synchronous and Asynchronous Inputs Synchronous inputs of a flip-flop only affect the output on the active clock edge. Asynchronous inputs of a flip-flop change the output immediately. Asynchronous inputs override synchronous inputs.

69. 69 Flip-Flop Asynchronous Inputs Preset: –An asynchronous set function, usually designated as Clear: –An asynchronous reset function, usually designated as Both Preset and Clear usually have LOW input active levels.

70. 70 Flip-Flop Asynchronous Inputs

71. 71 CLKJKQ t+1 Function 01XXX10PRESET 10XXX01Clear 00XXX11Forbidden 11Flip-Flop Operates Synchronously JK Flip-Flop Asynchronous Inputs Function Table

72. 72 JK Flip-Flop Asynchronous Inputs Function Table

73. 73 Unused Preset and Clear Inputs Disable by connecting to a logic HIGH (for active-LOW inputs). In Quartus II the asynchronous inputs of all flip-flop primitives are set to a default level of HIGH.

74. 74 Master Reset An asynchronous input used to set a sequential circuit to a known initial state. Usually a RESET tied to the inputs of all flip-flops. When activated, the output of the sequential circuit goes LOW.

75. 75 Master Reset

76. 76 Master Reset

77. 77 T (Toggle) Flip-Flop Output toggles on each applied clock pulse when a synchronous input is active. Synchronous input is designated as ‘T’.

78. 78 T (Toggle) Flip-Flop

79. 79 CLKTQ t+1 Function ↑0No change ↑1Toggle 0X QtQt Inhibited 1X QtQt ↓XQtQt T Flip-Flop Function Table

80. 80 T Flip-Flop Function Table

81. 81 Flip-Flops in PLDs Flip-flops are usually found in PLDs as registered outputs. A registered output of a PLD is defined as an output having a flip-flop (usually D-type) that stores the output state.

82. 82 Generic Array Logic (GAL) GAL: –A PLD whose outputs can be configured as combinational or registered Programming matrix is designed with electrically erasable logic cells.

83. 83 Generic Array Logic – Macrocell I/O circuit that can be configured as a registered output, a combinational output, or a dedicated input as required. Outputs can also be specified as active- HIGH or active-LOW.

84. 84 Generic Array Logic – Macrocell

85. 85 Generic Array Logic – Macrocell

86. 86 Generic Array Logic – Macrocell

87. 87 MAX 7000S CPLD – 1 Max 7000 CPLD family of devices is manufactured by Altera. EPM7128SLC84-7 is one of two devices installed on the UP-1 and UP-2 Boards. The device is in-circuit programmable.

88. 88 MAX 7000S CPLD – 2 Constructed of a series of Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Each LAB has 16 macrocells with similar I/O and programming capability to a low-density PLD. Refer to Figure 8.87 of the text.

89. 89 EPM7128SLC84-7 EPM7Max 7000 FAMILY 128Number of macrocells SIn-system programmable 8484-pin PLCC package 7Speed grade

90. 90 FunctionPins V CC 8 Ground8 JTAG port4 GCLK11 OE11 GCLRn1 GCLK2/OE21 User I/Os60 Total pins84 EPM7128SLC84-7 Pin Summary

91. 91 FLEX 10K CPLD – 1 Volatile: –Does not retain stored information after the power has been removed PLD based on look-up table architecture (LUT). A number of storage elements are used to synthesize logic functions by storing each function as a truth table.

92. 92 FLEX 10K CPLD – 2

93. 93 FLEX 10K CPLD – 3

94. 94 FLEX 10K Logic Element (LE) Performs a function similar to that of a macrocell in SOP-type PLDs. A 16-bit storage element that has circuitry to select various control functions.

95. 95 LE Control Functions Clock and reset. Flip-flop register outputs. Cascade and carry. Interconnections to local and global busses.

96. 96 LE Control Functions

97. 97 EPF10K70RC240-4 On the UP-2 board. 468 LABs (3744 Logic Elements). 9 EABs (18,432 bits).

98. 98 EPF10K70RC240-4