1. March 4, 2011. 1ENGI 5951 – Mechatronics II FPGA Based Interfaces for Smart Sensors and Actuators

2. What is an FPGA? A Field-Programmable Gate Array (FPGA) is a digital integrated circuit that can be customized by the designer “in the field” using a Hardware Description Language. FPGAs contain thousands of components called "logic blocks“ that can be “wired together” through a hierarchy of reconfigurable interconnects. March 4, 2011. 1ENGI 5951 – Mechatronics II

3. What is an FPGA? Modern FPGAs can have on the order of 200K Logic Cells. A simplified representation of a Logic Cell is shown below. March 4, 2011. 1ENGI 5951 – Mechatronics II

4. Quadrature Decoder/Counter Interface for Optical Encoder: State Machine March 4, 2011. 1ENGI 5951 – Mechatronics II

5. Optical Encoder March 4, 2011. 1ENGI 5951 – Mechatronics II

6. Optical Encoder - Decoding March 4, 2011. 1ENGI 5951 – Mechatronics II

7. Optical Encoder – State Diagram March 4, 2011. 1ENGI 5951 – Mechatronics II

8. Optical Encoder – Edge Detection Circuitry March 4, 2011. 1ENGI 5951 – Mechatronics II

9. Summary of Quadrature Decoding Logic State Transition Encoder Signals Flipflop outputs: enc_decX.q Past State Present State Count Chan A Chan B 0123 12UP1  1110 23  10111 34 0  0001 41  01000 14DOWN  00100 43 0  0010 32  11011 21 1  1101 Note:  and  indicate a rising and falling edge respectively. March 4, 2011. 1ENGI 5951 – Mechatronics II

10. Truth Table Implementation of Quadrature Decoder TABLE enc_dec[3..0].q=> dwn_cnt, up_cnt; B"0000"=>0,0; B"0001"=>0,1; B"0010"=>1,0; B"0011"=>0,0; B"0100"=>1,0; B"0101"=>0,0; B"0110"=>0,0; B"0111"=>0,1; B"1000"=>0,1; B"1001"=>0,0; B"1010"=>0,0; B"1011"=>1,0; B"1100"=>0,0; B"1101"=>1,0; B"1110"=>0,1; B"1111"=>0,0; END TABLE; March 4, 2011. 1ENGI 5951 – Mechatronics II

11. AHDL Implementation of Counter Module IF up_cnt THEN encoder[].d = encoder[].q + 1; ELSE IF dwn_cnt THEN encoder[].d = encoder[].q - 1; ELSE encoder[].d = encoder[].q; END IF; March 4, 2011. 1ENGI 5951 – Mechatronics II

12. Stepper Motor Controller: Synchronous Counter Design March 4, 2011. 1ENGI 5951 – Mechatronics II

13. Stepper Motor Half-Step Switching Sequences STEP TRANSISTORS 1234 1ONOFFONOFF 2ONOFF 3ONOFF ON 4OFF ON 5OFFONOFFON 6OFFONOFF 7 ON OFF 8 ONOFF March 4, 2011. 1ENGI 5951 – Mechatronics II

14. Truth Table for Half-Stepping Switching Sequence March 4, 2011. 1ENGI 5951 – Mechatronics II

15. Stepper Motor: Synchronous Counter Design March 4, 2011. 1ENGI 5951 – Mechatronics II

16. Schematic of stepper motor controller Stepper Motor: Synchronous Counter Design March 4, 2011. 1ENGI 5951 – Mechatronics II

17. Pulse-Width Modulation: VHDL/AHDL Programming March 4, 2011. 1ENGI 5951 – Mechatronics II

18. AHDL Implementation of PWM Controller totaltime[].clk = clk; totaltime[].clrn= VCC; totaltime[].prn = VCC; totaltime[].ena = io_space_2 & (add_latch[3..0].q == B"0110") & !write/; totaltime[].d= add_data[]; lowtime[].clk = clk; lowtime[].clrn= VCC; lowtime[].prn = VCC; lowtime[].ena = io_space_2 & (add_latch[3..0].q == B"0111") & !write/; lowtime[].d= add_data[]; March 4, 2011. 1ENGI 5951 – Mechatronics II

19. cntr[].clk = clk; cntr[].clrn= !(cntr[].q == totaltime[].q); cntr[].prn = VCC; cntr[].ena= VCC; cntr[].d= cntr[].q + 1; switch.clk= clk; switch.clrn= VCC; switch.prn = VCC; switch.ena = VCC; pwm_out= switch.q; switch.d = (cntr[].q < lowtime[].q); AHDL Implementation of PWM Controller March 4, 2011. 1ENGI 5951 – Mechatronics II

20. Conclusions CPLDs are well suited to the implementation of interfaces for smart sensors and actuators. Incorporating a CPLD that supports In-System Programmability (ISP) into a data acquisition system provides reconfigurable digital I/O that allows the target system to be reprogrammed by the user for a variety of applications without hardware modifications. This is particularly useful for those applications that require hardware interfaces for several different sensors simultaneously. March 4, 2011. 1ENGI 5951 – Mechatronics II