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Stonewalled Progress of Computing Efficiency 1 Reiner Hartenstein (keynote) SA - Sep 1 16:10 - 16:50

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Presentation on theme: "Stonewalled Progress of Computing Efficiency 1 Reiner Hartenstein (keynote) SA - Sep 1 16:10 - 16:50"— Presentation transcript:

1 Stonewalled Progress of Computing Efficiency http://hartenstein.de reiner@hartenstein.de 1 Reiner Hartenstein (keynote) SA - Sep 1 16:10 - 16:50 http://xputer.de/UnB/Reiner-SBCCI-12.pdf

2 © 2012, reiner@hartenstein.de http://hartenstein.de TU Kaiserslautern 2 x y *> Declarations HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag; goto PixMap[1,1] HalfZigZag; SouthWestScan uturn (HalfZigZag) HalfZigZag data counter HalfZigZag EastScan is step by [1,0] end EastScan; SouthWestScan is loop 8 times until [1,*] step by [-1,1] endloop end SouthWestScan; SouthScan is step by [0,1] endSouthScan; NorthEastScan is loop 8 times until [*,1] step by [1,-1] endloop end NorthEastScan; Flowware language example ( MoPL ) JPEG zigzag scan pattern http://xputer.de/GAG/ 37

3 © 2012, reiner@hartenstein.de http://hartenstein.de TU Kaiserslautern Duality of procedural Languages Flowware Languages read next data item goto (data address) jump to (data address) data loop data loop nesting data loop escape data stream branching yes: internally parallel loops 3 Software Languages read next instruction goto (instruction address) jump to (instruction address) instruction loop instruction loop nesting instruction loop escape instruction stream branching no: internally parallel loops Asymmetry But there is an Asymmetry program counter: data counter(s): more simple: no ALU tasks no tunnel view!


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