Chapter 12: Analog Converter Subsystem

Chapter 12: Analog Converter Subsystem
Esteban Rodriguez-Marek Eastern Washington University Department of Engineering & Design Introduction. Thank the Engineering Forum for this opportunity. Talk a little bit about yourself.

The Analog Converter Subsystem
A digital-to-analog converter (D/A or DAC) takes a digital input and produces a corresponding analog voltage (or current). An analog-to-digital converter (A/D or ADC) produces a digital number corresponding to an analog input voltage sample. The 68HC11 has a built-in A/D but does not have a built-in D/A. It can, however, easily be interfaced to an external D/A converter IC. 2 of 68

Concepts and Terminology
Analog signals have a ratio metric range. These range from a low value to a high value. For example: 0V to 5V -2.5V to +12.5V 4mA to 20mA A binary code can represent the percentage of any analog range. For example, $00 (0% of full range) represents 0V and $FF (almost) represents 5V, for an 8-bit binary code. 3 of 68

Concepts and Terminology
Generally, the binary number system that represents the analog range is unsigned. A number with all zeros represents the lowest analog value in the range, and a binary number with all ones represents the highest value. A binary number whose most-significant digit is one with the rest being zeros represents the middle of the analog range. 4 of 68

MC68HC Chip pin assignments (E series)
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Definitions Offset: Minimum analog value.
Span: Difference (range) of maximum and minimum analog values. Weight: Analog value corresponding to a particular bit in the binary number. Step size: Span / 2n, where n is the number of bits in the corresponding digital code Note: n – 1 = bit position of MSB; n = 0 for a 1-bit number 6 of 68

Definitions Resolution: Same as step size. It is the smallest analog change resulting from changing one bit in the digital number. It is also the weight of the LSB. Sometimes resolution is specified as the number of bits (n). 7 of 68

Equations Analog number , Nanalog:
Where NDIGITAL should be in decimal number Note: 1. These equations hold true as long as the numbers are within range. 2. Step size = Span / 2n 8 of 68

Examples The following illustrates the use of definitions and equations. Consider an analog range of 0 to +25.6V. The 8-bit digital range is $00 to $FF. It can also be said that the resolution is 8-bits (n = 8). Offset = 0V Span = 25.6V – 0V = 25.6V 9 of 68

Analog Range to 8-bit Digital Conversion
Examples Bit Weights for 0V to +25.6V Analog Range to 8-bit Digital Conversion Digital bit Bit weight (V) 7 25.6 X 2-1 = 25.6 / 2 = 12.8 6 25.6 X 2-2 = 25.6 / 4 = 6.4 5 25.6 X 2-3 = 25.6 / 8 = 3.2 4 25.6 X 2-4 = 25.6 / 16 = 1.6 3 25.6 X 2-5 = 25.6 / 32 = 0.8 2 25.6 X 2-6 = 25.6 / 64 = 0.4 1 25.6 X 2-7 = 25.6 / 128 = 0.2 25.6 X 2-8 = 25.6 / 256 = 0.1 10 of 68

to Digital Conversion Table
Examples 0V to 25.6V Analog Range to Digital Conversion Table Analog (V) Digital (hex) 00 3.2 20 6.4 40 9.6 60 12.8 80 16.0 A0 19.2 C0 22.4 E0 25.5 FF Outside the Range If the input of an A/D is below the minimum or above the maximum of the range, the corresponding digital value will be minimum or maximum respectively. 11 of 68

Signal Conditioning negative values positive voltages greater than 5
Signal conditioning is sometimes necessary because raw sensor data outputs are not always suitable for analog-to-digital conversion. The A/D input of the 68HC11 typically will be in the range of 0 to 5V so signal conditioning will be needed if the actual data has any of the following characteristics: negative values positive voltages greater than 5 very small voltages either positive or negative currents alternating voltages or currents Signal conditioning may also be required if there is a need to buffer (isolate) the sensor output from the A/D converter input or for noise reasons. 12 of 68

Digital-To-Analog Converters
Many digital-to-analog converters (D/As) use an R-2R ladder network. It is called that because the resistors are connected in a pattern that resembles a ladder. There are two resistor values used in the circuit: some resistors have the value R and the others are twice that value or 2R. A D/A IC has the ladder circuit, switches, and operational amplifier built into it. The switches are analog switches controlled by digital signals. 13 of 68

An analog switch is a special type of transistor circuit that acts like a switch for analog signals. The output voltage VO is proportional to the binary input. Each branch of the ladder network contributes current whose value is proportional to the bit weight of that branch. The amplifier circuit sums the current components to produce a voltage proportional to the binary input. 14 of 68

R/2R ladder with switch inputs. Assume that SW4 was moved to +V 15 of 68

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A similar analysis is applied to the case of SW3 was moved to +V. For SW2 case, Vout = V/8 For SW1 case, Vout = V/16 18 of 68

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Waveform Generation Using a D/A, a processor can theoretically generate any type of waveform. Each new output can be calculated or looked up in a table. Since the outputs are in discrete steps, a low-pass filter can smooth the waveform. There is, however, an upper limit to the frequency of the generated waveform because it takes time for the CPU to calculate a new digital number and output it to the D/A. Assuming that the system takes 256 steps to represent the swing from minimum to maximum signal value, it will take 2.56 ms (256 X 20E X 0.5 s/E) for each waveform cycle. (for 20 instruction cycles in total) The maximum signal frequency is then roughly 390Hz (i.e., 1/2.56ms). 20 of 68

On-Chip D/A Some versions of the 68HC11 have a built-in D/A subsystem that converts 8-bit digital data to a corresponding analog voltage. The subsystem outputs an analog voltage between supply voltages VSS and VDD. based on the byte in the data register. It works on the R-2R ladder principal. 21 of 68

Ladder circuit for our lab
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Analog-To-Digital Converters
There are several different techniques used by analog-to-digital converters to perform the conversion: Successive Approximation – offers medium conversion speed and is the most common general-purpose A/D conversion method. Integration – is used in digital meters for its good accuracy and noise immunity, but is relatively slow. Flash or Simultaneous – is extremely fast, so it is used in applications such as digital video processing. On the downside, the circuitry is expensive. Sigma-Delta – is a complex technique with very good resolution and relatively slow speed. 23 of 68

Successive Approximation
It works by guessing a value for the digital code and then checking the guess to see if it was right. It checks the guess by sending the digital code to a built-in D/A converter an comparing the output of the D/A converter to the analog input signal. If the two analog voltages are the same, the guess was right, otherwise it was wrong. 24 of 68

If it was wrong, the A/D converter can tell whether it was too high or too low. The successive approximation does not make random guesses. Its first guess is $80, or the middle value of the analog input range. If the guess was too high, the next guess is $40 and so on. 25 of 68

Each guess narrows the range that needs to be considered by one-half, so the maximum number of guesses needed for an 8-bit digital result is eight. If the guess is too low, the guess bit remains a 1, otherwise it is changed to a 0. A conversion complete signal is asserted when the result is correct. 26 of 68

Example Successive Approximation Conversion
An example Ex) The analog input voltage is 2.2V. The analog range is 0 to 10V. The step size is 0.039V or 39mV Example Successive Approximation Conversion Guess # Guess D/A output (V) Conclusion Digital code 1 4.992 high 2 2.496 3 1.248 low 4 1.872 5 2.184 6 2.340 7 2.262 8 2.223 done 27 of 68

Ranges for previous Example By Guess
An example Ranges for previous Example By Guess Guess # VIN possibilities Range 1 0.000 < VIN < 4.992 4.992 2 0.000 < VIN < 2.496 2.496 3 1.248 < VIN < 2.496 1.248 4 1.872 < VIN < 2.496 0.624 5 2.184 < VIN < 2.496 0.312 6 2.184 < VIN < 2.340 0.156 7 < VIN < 2.262 0.078 8 2.184 < VIN < 2.223 0.039 Note: In this table, VIN may equal one of the two boundary values. 28 of 68

The Built-In A/D Subsystem
The 68HC11’s built-in A/D converter uses a charge redistribution successive approximation circuit to perform the conversion. (clock and charge pump are required) A network of capacitors connected to a comparator The capacitors are switched into different configurations (a sample mode, hold mode, and approximation mode) The A/D subsystem is relatively easy to use compared to the other I/O subsystems. It has eight inputs at port E called channels. Depending on configuration of subsystem registers, the software can read any of the eight possible inputs. 29 of 68

MC68HC11E9 Block diagram 30 of 68

MC68HC11E9 ADC 31 of 68

Registers related to A/D subsystem
Data Registers Conversion result registers – ADR1(at $1031) through ADR4 (at $1034) Control Registers A/D control register – ADCTL (at $1030) System options register – OPTION (at $1039) Status Registers There are no dedicated status registers for this subsystem. 32 of 68

Data registers related to A/D subsystem
$1031 ADR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $1032 ADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $1033 ADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $1034 ADR4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 33 of 68

Control registers related to A/D subsystem
$1030 ADCTL CCF - SCAN MULT CD CC CB CA $1039 OPTION ADPU CSEL IRQE DLY CME - CR1 CR0 34 of 68

Charge Pump and Oscillator
The software initialization procedure for the A/D includes enabling the charge pump and defining the conversion clock source. To enable the charge pump, the A/D power-up bit (ADPU) in the system configuration options register (OPTION) must be set. After enabling the charge pump, the MCU should wait at least 100s before using the A/D converter. 35 of 68

Charge Pump and Oscillator
The successive approximation circuit can use the system clock (E) if it is greater than 750kHz. To select E as the clock source, the clock select bit (CSEL) in register OPTION must be cleared. To select an internal RC oscillator (approximately 2MHz), set the CSEL bit. 36 of 68

Quantization Error 37 of 68

Quantization Error 38 of 68

Example Initialization Routine
* Initialization subroutine for A/D REGBAS EQU $ ;Starting address for register block OPTION EQU $39 ;options register ORG $180 * Subroutine STARTAD. Powers up A/D. Must be run before using it after * reset or a power-down sequence. In this case, uses E clock as source. * No calling or return registers except CCR affected STARTAD PSHX ;preserve IX LDX #REGBAS ;point to registers BSET OPTION,X $80 ;ADPU = 1 to power up ;(M+mm to M) BCLR OPTION,X $40 ;CSEL = 0 to select E clock ;(Mmm’ to M) JSR DLY100 ;wait 100 us PULX ;restore IX RTS ;return 39 of 68

Reference Voltages and Channels
The voltage at the analog reference high pin (VRH) sets the analog value for digital data $FF. In other words, it sets the upper limit of the analog range. Similarly, the voltage at the analog reference low pin (VRL) sets the low limit of the range, the analog value of $00. The A/D subsystem can use any of the eight port E inputs to read analog signals. Each pin is known as a channel. Pin PE0 is channel zero (AN0), and so on. Channels AN4 through AN7 are not available in some 68HC11 models. 40 of 68

MC68HC Chip pin assignments (E series)
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Reference Voltages and Channels
The subsystem can operate in either single-channel or multi-channel mode as selected by the multiple-channel control bit (MULT) in A/D control register (ADCTL). For either mode, the subsystem performs four conversions requiring 32 cycles each. At the end of each conversion it puts the digital data in a result register. The result registers are updated in sequential order (ADR1, ADR2, ADR3, ADR4). After conversion is done, the MCU sets the conversion complete flag (CCF) in register ADCTL. 42 of 68

Channel Selection The CD, CC, CB, CA bits are used to specify the channel(s) to be operated on for an A/D conversion operation. When a multiple-channel mode is selected (i.e., MULT=1), the CB and CA selects have no effect, and the group of four channels affected are selected by CD and CC. 43 of 68

Single-Channel Operation
If the software clears bit MULT, the subsystem operates in single-channel mode. Only one channel is used, and its result is placed in all four result registers when conversion is complete. Any of the channels can be configured as the one to be used for single-channel mode. Actually, the subsystem performs four conversions and places their results sequentially in each result register. After the four conversions are complete, the A/D sets the CCF. 44 of 68

The software can do two things now: read any result register to obtain the digital code. read all four and average The subsystem can perform four conversions once or perform them continuously. The continuous scan control bit (SCAN) in control register ADCTL determines which one it does. SCAN=0: A/D performs 4 conversions and stops. SCAN=1: A/D performs conversions continuously. 45 of 68

To start conversion, the application program writes to control register ADCTL: Example: STAA ADCTL,X To read the result, the program must poll flag bit CCF (no interrupt available) to determine when conversion is complete. When the flag has set, the program reads any result register. READ BRCLR ADCTL, X $80 READ LDAA ADR4, X ;Could be any ADR 46 of 68

For continuous scan conversion, the application program can obtain a new result simply by reading a result register at any time. If continuous scan was not selected, the software must repeat the procedure to start conversion and wait for the flag to set. Flag CCF is cleared automatically every time (any) data is written to register ADCTL. 47 of 68

* Initialization subroutine for A/D REGBAS EQU $ ;Starting address for register block OPTION EQU $39 ;options register ORG $180 * Subroutine STARTAD. Powers up A/D. Must be run before using it after * reset or a power-down sequence. In this case, uses E clock as source. * No calling or return registers except CCR affected STARTAD PSHX ;preserve IX LDX #REGBAS ;point to registers BSET OPTION,X $80 ;ADPU = 1 to power up BCLR OPTION,X $40 ;CSEL = 0 to select E clock JSR DLY100 ;wait 100 us PULX ;restore IX RTS ;return 48 of 68

Example of Single-channel Operation
REGBAS EQU $ ;Starting address for register block ADCTL EQU $30 ADR4 EQU $34 ORG $180 * Subroutine INAD. I/O handler routine for analog input using * continuous scan. Calling program must execute this subroutine after * Subroutine STARTAD (Listing 12.1) and before reading analog result. * Suppose ACCA has channel number (e.g. xxxx0011 for PE3 channel) INAD ANDA #$07 ;ensure that bits 3 to 7 clear * ;note that others select channel ORAA #$20 ;SCAN=1, MULT=0 STAA ADCTL,X ;start conversion * ;also clears CCF * wait for first conversion done INAD1 BRCLR ADCTL,X $80 INAD1 * ;CCF set at this point LDAA ADR4,X ;read any result register * ;in this case, the most recent RTS ;return 49 of 68

Comment on the example After the application program has called the subroutine once, it can read any result register at any time to obtain a new analog result. (i.e. just call reading subroutine such as “INAD1” after clearing CCF) For non-continuous scan conversion, a similar subroutine can be used. The subroutine will not have the ORAA instruction in INAD subroutine. The application program will have to call “INAD” and “INAD1” each time it wants a new analog result. 50 of 68

Multi-channel Operation
If the software sets bit MULT in register ADCTL, the subsystem operates in multi-channel mode. In this mode, either the first four channels (AN0 to AN3) or the last four channels (AN4 to AN7) are converted. The subsystem sets the conversion complete flag after the four result registers have been updated. Like single-channel operation, there is the option of using continuous conversion. 51 of 68

* Initialization subroutine for A/D REGBAS EQU $ ;Starting address for register block OPTION EQU $39 ;options register ORG $180 * Subroutine STARTAD. Powers up A/D. Must be run before using it after * reset or a power-down sequence. In this case, uses E clock as source. * No calling or return registers except CCR affected STARTAD PSHX ;preserve IX LDX #REGBAS ;point to registers BSET OPTION,X $80 ;ADPU = 1 to power up BCLR OPTION,X $40 ;CSEL = 0 to select E clock JSR DLY100 ;wait 100 us PULX ;restore IX RTS ;return 52 of 68

Multi-Channel example (1)
* Subroutine INMAD. I/O handler routine for analog input using * continuous scan and multiple-channel operation. Assume A has $04 * and TADR4 is the reserved memory. * Calling registers * IX = register block address * ACCA = $00 to select channels AN0 to AN3 * ACCA = $04 to select channels AN4 to AN7 * C = 1 if error, otherwise 0 ORG $180 INMAD PSHA ;preserve ACCA if no error CMPA #$00 ;check if ACCA is legal BEQ INMAD1 CMPA #$04 BNE INMAD3 ;exit to return error code 53 of 68

* if not legal INMAD1 ORAA #$30 ;SCAN=1, MULT=1 STAA ADCTL,X ;start conversion * ;also clears CCF * wait for first conversion done INMAD2 BRCLR ADCTL,X $80 INMAD2 ;CCF set at this point LDAA ADR4,X STAA TADR ;Save it into reversed memory ; If need other channels, repeat LDAA, STAA ; with different storage addresses. 54 of 68

* return section if no error PULA ;restore ACCA CLC ;C=0 for no error RTS ;return results * return section if error INMAD3 SEC ;C=1 for error RTS ;and return 55 of 68

Practical Considerations
The HC11 does not come with a capacitor between VRH and VRL. Wytec board includes one, as recommended by Motorola. 56 of 68

An even better solution is to connect a low pass filter to the I/O connector: 57 of 68

A current limiting resistor (between 1kW and 10kW) is included in the A/D input pin. Without this, the ADC’s input could be permanently damaged. Problems could arise by large voltages and with negative voltages. 58 of 68

A model of each input is shown: Large voltages will force zener to avalanche. Negative voltages will forward-bias it. Recommended current is 25 mA. 59 of 68

A model of each input is shown: Large voltages will force zener to avalanche. Negative voltages will forward-bias it. Recommended current is 25 mA. 60 of 68

Limiting resistor shown: 61 of 68

Example: Problem Statement
Assume: A/D’s full-range input is 5.12 V. Limiting resistor R=10kW. Worst-case input leakage current of 400nA flows. Determine input offset voltage. 62 of 68

Example: Solution Each binary count is: 5.12/256 = 20 mV = 1 LSB
(where LSB means the converter’s LSB’s value in volts) Leakage current produces an error of: (400nA)(10kW) = 4 mV In terms of LSB: (4mV)/(20mV/LSB) = 0.2 LSB. 63 of 68

Example: Notes This example shows that it is possible to double R to 20 kW and still not reach an error of 0.5 LSB However, large R values may be problematic, due to errors not accounted for (i.e. resistor’s tolerance, temperature changes, noise, etc). 64 of 68

Example Assume a -15V accidentally touches the ADC input. Will Iin<25mA if limiting resistor = 1kW? Diode is forward biased, thus (15-.7)/1k=14.3 mA < 25mA NOTE: Small R results in permanent damage. Large R results in conversion errors! 65 of 68

Sample Connection 66 of 68

Improving Accuracy Accuracy of ADC is diminished when input signals are close to supply rail. To overcome this: Raise VRL above GND to 0.5 V. Lower VRH below VDD to 4.5 V. 67 of 68

Improving Accuracy 68 of 68

Chapter 12: Analog Converter Subsystem

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