1. VERILOG EXAMPLES

2. //example 1.1 module ffNand; wireq, qBar; regpreset, clear; nand #1 g1 (q, qBar, preset), g2 (qBar, q, clear); endmodule

3. //example 1.2 module ffNandSim; wireq, qBar; regpreset, clear; nand #1 g1 (q, qBar, preset), g2 (qBar, q, clear); initial begin // two slashes introduce a single line comment $monitor ($time,, "Preset = %b clear = %b q = %b qBar = %b", preset, clear, q, qBar); //waveform for simulating the nand flip flop # 10 preset = 0; clear = 1; # 10 preset = 1; # 10 clear = 0; # 10 clear = 1; # 10 $finish; end endmodule

5. //example 1.3 module m16 (value, clock, fifteen, altFifteen); output[3:0]value; outputfifteen, altFifteen; inputclock; dEdgeFFa (value[0], clock, ~value[0]), b (value[1], clock, value[1] ^ value[0]), c (value[2], clock, value[2] ^ &value[1:0]), d (value[3], clock, value[3] ^ &value[2:0]); assign fifteen = value[0] & value[1] & value[2] & value[3]; assign altFifteen = &value; endmodule

6. //examples 3.2 and 1.4 module dEdgeFF (q, clock, data); outputq; regq; inputclock, data; initial #10 q = 0; always (@negedge clock) #10 q = data; endmodule

8. //example 1.6 module board; wire[3:0]count; wireclock, f, af; m16counter (count, clock, f, af); m555clockGen (clock); always @ (posedge clock) $display ($time,,,"count=%d, f=%d, af=%d", count, f, af); endmodule

11. // example 1.8 module m16Behav (value, clock, fifteen, altFifteen); output[3:0]value; reg [3:0] value; outputfifteen, altFifteen; regfifteen, altFifteen; inputclock; initial value = 0; always begin (@negedge clock) #10 value = value + 1; if (value == 15) begin altFifteen = 1; fifteen = 1; end else begin altFifteen = 0; fifteen = 0; end endmodule

18. //example 4.1 module fullAdder(cOut, sum, aIn, bIn, cIn); outputcOut, sum; inputaIn, bIn, cIn; wirex2; nand(x2, aIn, bIn), (cOut, x2, x8); xnor(x9, x5, x6); nor(x5, x1, x3), (x1, aIn, bIn); or(x8, x1, x7); not(sum, x9), (x3, x2), (x6, x4), (x4, cIn), (x7, x6); endmodule