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Computer Architecture Vector Architectures Ola Flygt Växjö University http://w3.msi.vxu.se/users/ofl/ Ola.Flygt@msi.vxu.se +46 470 70 86 49

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Outline Introduction Basic priciples Sd Examples Cray xcx CH01

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Scalar processing 4n clock cycles required to process n elements! Timeop 0a0a0 4a1a1 8a2a2 …… 4nanan

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Pipelining 4n/(4+n) clock cycles required to process n elements! Timeop 0 op 1 op 2 op 3 0a0a0 1a1a1 a0a0 2a2a2 a1a1 a0a0 3a3a3 a2a2 a1a1 a0a0 4a4a4 a3a3 a2a2 a1a1 …………… nanan a n-1 a n-2 a n-3

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Pipeline Basic Principle Stream of objects Number of objects = stream length n Operation can be subdivided into sequence of steps Number of steps = pipeline length p Advantage Speedup = pn/(p+n) Stream length >> pipeline length Speedup approx.p Speedup is limited by pipeline length!

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Vector Operations Operations on vectors of data (floating point numbers) Vector-vector V1 <-V2 + V3 (component-wise sum) V1 <-- V2 Vector-scalar V1 <-c * V2 Vector-memory V <-A (vector load) A <-V (vector store) Vector reduction c <-min(V) c <-sum(V) c <-V1 * V2 (dot product)

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Vector Operations, cont. Gather/scatter V1,V2 <-GATHER(A) load all non-zero elements of A into V1 and their indices into V2 A <-SCATTER(V1,V2) store elements of V1 into A at indices denoted by V2 and fill rest with zeros Mask V1 <-MASK(V2,V3) store elements of V2 into V1 for which corresponding position in V3 is non-zero

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Example, Scalar Loop approx. 6n clock cycles to execute loop. Fortran loop: DO I=1,N A(I) = A(I)+B(I) ENDDO Scalar assembly code: R0 <- N R1 <- I JMP J L: R2 <- A(R1) R3 <- B(R1) R2 <- R2+R3 A(R1) <- R2 R1 <- R1+1 J: JLE R1, R0, L

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Example, Vector Loop 4n clock cycles, because no loop iteration overhead (ignoring speedup by pipelining) Fortran loop: DO I=1,N A(I) = A(I)+B(I) ENDDO Vectorized assembly code: V1 <- A V2 <- B V3 <- V1+V2 A <- V2

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Chaining Overlapping of vector instructions (see Hwang, Figure 8.18) Hence: c+n ticks (for small c) Speedup approx.6 (c=16, n=128, s=(6*128)/(16+128)=5.33) The longer the vector chain, the better the speedup! A <-B*C+D chaining degree 5 Vectorization speedups between 5 and 25

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Vector Programming How to generate vectorized code? 1. Assembly programming. 2. Vectorized Libraries. 3. High-level vector statements. 4. Vectorizing compiler.

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Vectorized Libraries Predefined vector operations (partially implemented in assembly language) VECLIB, LINPACK, EISPACK, MINPACK C = SSUM(100, A(1,2), 1, B(3,1), N) 100...vector length A(1,2)...vector address A 1...vector stride A B(3,1)...vector address B N...vector stride B Addition of matrix column to matrix row.

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High-Level Vector Statements e.g. Fortran 90 INTEGER A(100), B(100), C(100), S A(1:100) = S*B(1:100)+C(1:100) * Vector-vector operations. * Vector-scalar operations. * Vector reduction. *... Easy transformation into vector code.

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Vectorizing Compiler 1. Fortran 77 DO Loop * DO I=1, N D(I) = A(I)*B+C(I) ENDDO 2. Vectorization * D(1:N) = A(1:N)*B+C(1:N) 3. Strip mining * DO I=1, N/128 D(I:I+127) = A(I:I+127)*B + C(I:I+127) ENDDO IF ((N.MOD.128).NEQ.0) A((N/128)*128+1:N) =... ENDIF 4. Code generation * V0 <- V0*B... Related techniques for parallelizing compiler!

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Vectorization In which cases can loop be vectorized? DO I = 1, N-1 A(I) = A(I+1)*B(I) ENDDO | V A(1:128) = A(2:129)*B(1:128) A(129:256) = A(130:257)*B(129:256).... Vectorization preserves semantics.

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Loop Vectorization s semantics always preserved? DO I = 2, N A(I) = A(I-1)*B(I) ENDDO | V A(2:129) = A(1:128)*B(2:129) A(130:257) = A(129:256)*B(130:257).... Vectorization has changed semantics!

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Vectorization Inhibitors Vectorization must be conservative; when in doubt, loop must not be vectorized. Vectorization is inhibited by Function calls Input/output operations GOTOs into or out of loop Recurrences (References to vector elements modified in previous iterations)

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Components of a vectorizing supercomputer

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The DS for floating-point precision

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The DS for integer precision

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How vectorization works Un-vectorized computation

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How vectorization works vectorized computation

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How vectorization speeds up computation

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Speed improvements Non-pipelined computation

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Speed improvements pipelined computation

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Increasing the granularity of a pipeline Repetition governed by slowest component

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Increasing the granularity of a pipeline Granularity increased to improve repetition

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Parallel computation of floating point and integer results

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Mixed functional and data parallelism

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The DS for parallel computational functionality

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Performance of four generations of Cray systems

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Communication between CPUs and memory

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The increasing complexity in Cray systems

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Integration density

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Convex C4/XA system

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The configuration of the crossbar switch

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The processor configuration

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Computer Architecture SIMD Ola Flygt Växjö University +46 470 70 86 49.

Computer Architecture SIMD Ola Flygt Växjö University +46 470 70 86 49.

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