1. Synthesis for Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur

2. Dec 21,2007 SfT@iitk 2 Testability Objective  Improve  Controllability  Observability  Reduction in sequential depth  Elimination of sequential loop

3. Dec 21,2007 SfT@iitk 3 Sequential Depth Reduction - Allocation Allocation Scheme  Enhance controllability and observability  Reduction in Sequential depth Based on RT Architecture Independent of Test Technology

4. Dec 21,2007 SfT@iitk 4 Controllability and Observability a b c d e f g h Lifetime table Allocation 1 R1: a, c, g R2: b, d, h R3: e R4: f

5. Dec 21,2007 SfT@iitk 5 Controllability and Observability a b c d e f g h Lifetime table Allocation 2 R1: a, c, R2: b, d R3: e, f R4: f, g

6. Dec 21,2007 SfT@iitk 6 Controllability and Observability If any one of variable assigned to a register is a PI (PO) of the chip, this register is directly controlled (observed); if not, register can be accessed through other registers Goal: To ensure that as many registers as possible in the implementation are assigned at least PI/PO Each row of register must cover a PI/PO TSR1: Whenever possible, allocate a register to at least one PI or PO

7. Dec 21,2007 SfT@iitk 7 Sequential Depth Reduction SDFG +1 +2 +3 0 1 a 2 bde c f g a b c d e f g Lifetime Table

8. Dec 21,2007 SfT@iitk 8 Sequential Depth Reduction TSR1 does not provide inform testability suggestions on module allocation and interconnect allocation Register allocation using TSR1 R = { (a,c,g), (b,f), (d), (e)} Two possible Module allocation M1 ={(+ 1,3 ), (+ 2 )} M2 ={(+ 1,2 ), (+ 3 )}

9. Dec 21,2007 SfT@iitk 9 Sequential Depth Reduction M1 is preferred to save interconnect cost output of +2 is hard to observe An error effect needs to propagate through an additional register R2 before it can be observed

10. Dec 21,2007 SfT@iitk 10 Sequential Depth Reduction R1R2 R4 R3 ab d e g R = { (a,f,g), (b,c), (d), (e)} TSR2: Reduce the sequential depth from an input register to an output register

11. Dec 21,2007 SfT@iitk 11 Sequential Depth Reduction R1R2 R4 R3 ab d e g R = { (a,c,g), (b,f), (d), (e)}

12. Dec 21,2007 SfT@iitk 12 Sequential Loop Reduction SDFG +1 +3 +2 1 2 3 R1(d) 4 R3(c) R2(b) R1(a) R1 R3 R2 Sequential Loop: Reuse of R1

13. Dec 21,2007 SfT@iitk 13 Sequential Loop Reduction +1 +6 +7 +2 +8 +3 +4 x1 x2 a 6 x9 TIME 1 TIME 2 TIME 3 TIME 4 +5 y e b f g c d TIME 5

14. Dec 21,2007 SfT@iitk 14 Sequential Loop Reduction Alloc scheme Register AllocationModule allocation #Mux#loopFC A1R1 =(x1,a), R2=(x4,e,b) R3= (x6,f,c), R4=(x7,d,g) R5= (x9,y) (+1,4) (+2,3) (+3,7) (+5,8) 19384 A2R1 =(x6,e,b,c,d,y), R2=(x1,a) R3= (x4,f), R4=(x7,g) R5= (x9) (+1,2) (+6) (+3,7) (+4,5,8) 160100

15. Dec 21,2007 SfT@iitk 15 Sequential Loop Reduction R1 R2 R5 R3 R4 A1

16. Dec 21,2007 SfT@iitk 16 Sequential Loop Reduction R1 R2 R5 R3 R4 A2

17. Dec 21,2007 SfT@iitk 17 Scheduling for Sequential Depth/Loop Reduction TSR3: Reduce Sequential loop by Proper resource sharing to avoid creating sequential loops for cyclic DFG Assign IO registers to break sequential loop TSR4: Schedule operations to support the application of TSR1, TSR2, and TSR3

18. Dec 21,2007 SfT@iitk 18 Controllability + *- a R (b) Primary input R(c) +* - R(a) R(b) Primary input R(c) 0 1 2 0 1 2 R = (b,c, …) Not directly controllable R = (a,b,c, …) Directly controllable

19. Dec 21,2007 SfT@iitk 19 Observability R 2 (z) R1 = (….,w,x, …) Not directly observable + * - t t+1 t+2 * R 1 (w) R 2 (y) R 1 (x) t+3 + * - t t+1 t+2 * R 1 (w) R 1 (y) R 1 (x) t+3 R 1 (z)

20. Dec 21,2007 SfT@iitk 20 Sequential Depth Reduction R 2 (z) *1 *2 - t t+1 t+2 + R 1 (w) R 2 (y) R 1 (x) t+3 R 2 (v) R 3 (s) R 3 (u) R 2 (z) *1 *2 - t t+1 t+2 + R 1 (w) R 2 (y) R 1 (x) t+3 R 2 (v) R 3 (s) R 3 (u)

21. Dec 21,2007 SfT@iitk 21 Mobility Path * * * + * * * +< - - 12 3 4 5 6 7 8 9 10 11 TIME 1 TIME 2 TIME 3 TIME 4

22. Dec 21,2007 SfT@iitk 22 Mobility Path * * * + - - TIME 1 TIME 2 TIME 3 TIME 4

23. Dec 21,2007 SfT@iitk 23 Mobility Path Scheduling Mobility_path_scheduling(G){ 1.ASAP_scheduling(G); 2.ALAP_scheduling(G); 3.Update_op_slack_and_mobility(G); 4.While (unscheduled_op(G) ≠ 0){ 5. P k = next_min_mobility_path(G); 6. partial scheduling(P k, G); 7. testMP(P k, G); / analyze testability on P k 8.} 9.}

24. Dec 21,2007 SfT@iitk 24 Mobility Path Scheduling partial_scheduling(P k,G){ 1.For each (operation o on Pk) 2. if (o.earliest = o.latest) // mobility becomes 0 3. o.active = o.earliest // assign schedule 4.Update_op_slack_and)mobility(G); 5.While (unscheduled_op (P k ) ≠ 0){ 6. (o, o.ll_cycles) = next_op_with _least_no_light_load_cycles(Pk, G); 7. o.active = most_preferred_cycle(o.ll_cycles, G);