1. Register Transfer Level
Chapter 8
Register Transfer Level

2. Content Register Transfer Level (RTL) RTL in HDL
Algorithmic State Machines (ASM)
Design Example
HDL Description of Design Example
Binary Multiplier
Control Logic
HDL Description of Binary Multiplier
Design with Multiplexers

3. Register Transfer Level (RTL)
Large Digital system design – modular approach
modular :constructed from digital device, e.g. register, decoder, multiplexer etc.
Register Transfer operation
The information flow and processing perform on the data stored in register
RTL is specified by the following three components:
The set of register in the system
The operation that are performed on the data stored in the register
The control that supervises the sequence of operation in the system

4. Register Register is constructed from F.F. and gates
1 F.F. =>1 bit register
N F.F. =>n bit resister
Register can perform set, cleared, or complement

5. Data processing in register
performed in parallel during one clock
The result may replace previous data or transferred to another register
For example
counter
Shift register

6. Statements of RTL Transfer: R2←R1 Conditional statement: Other
if (T1=1) then(R2 ← R1)
if(T1=1)then(R2 ← R1, R1 ← R2)
Other
R1 ←R1+R2
R3 ←R3+1
R4 ←shr R4
R5 ← 0

7. RTL in HDL Digital system can be described in RTL Verilog HDL
By means of HDL
Verilog HDL
RTL description use a combination of behavior and data flow

8. The transfer statement of Verilog HDL (without a clock)
Continuous statement:
Procedural assignment (without a clock):

9. The transfer statement of Verilog HDL (with a clock)
Blocking: use “=” as transfer operator
executed sequentially
non-blocking: use “<=” as transfer operator
executed on parallel

10. HDL operators Arithmetic :+ 、- 、 * 、 / 、 % Logical:&& 、 || 、!
Bitwise or reduction
Relational:> 、 < 、 == 、 != 、 >= 、 <=
True or false
Shift: >> 、 << 、 { , }

11. Loop statement Repeat,Forever,While,For
Must appear inside an initial or always block

12. Logic Synthesis
The automatic process of transforming a high-level language description such as HDL into an optimized netlist of gates that perform the operations specified by the source code
Designers adopt a vendor-specific style suitable for particular synthesis tools
HDL constructs used in RTL description can be converted into gate-level description

13. Example of synthesis from HDL to gate structure
Assign
assign Y = S ? I1:I0 ;
Is interpreted as a multiplexer of 2-to-1
always
may imply a combinational or sequential circuit
(I1 or I0 or S)
if (S) Y=I1 ;
else Y=I0 ;
(posedge clock)
(negedge clock)

14. Process of HDL simulation and synthesis

15. Algorithmic State Machine
Logic design can be divided into two part
The digital circuits that perform the data processing operation
Control circuits that determines the sequence in which the various actions are performed

16. Algorithmic State Machine (ASM)
A special flowchart that has been developed specifically to define digital hardware algorithms
Resembles a conventional flowchart, but is interpreted somewhat differently.
conventional: sequential
ASM:
sequence of even
timing relationship between the states of sequential controller
even occurs while going from one state to the next
Three basic elements: state box, decision box, conditional box

17. State box
FIGURE 8.3 ASM chart state box

18. Decision box
FIGURE 8.4 ASM chart decision box

19. Conditional box
FIGURE 8.5 ASM chart conditional box

20. ASM block

21. ASM chart and state diagram

22. Timing consideration
Major difference between conventional flow chart and a ASM chart is in interpreting the time relation among the various operation
ASM considers the entire block as one unit.

23. Design example Two F.F. E and F
A 4-bits binary counter A (A4,A3,A2 and A1)
A start signal S (starting by clearing A and F)
S=1, increment counter
A3 and A4 determine the sequences of operations
If A3 = 0, E is clear to 0, count continues
If A3 = 1,E is set to 1,then if A4 = 0, the count continues, but if A4 = 1, F is set to 1 on next clock pulse and system stops counting
Then if S = 0, the system remains in the initial state, but if S = 1, the operation cycle repeats.

24. ASM chart

25. Table 8-2

26. Datapath for Design Example

27. RTL Description

28. State table for control
Two F.F. G1 and G2

29. Logic diagram of control

30. HDL Description HDL Example 8-2
//RTL description of design example (Fig.8-11)
module Example_RTL (S,CLK,Cir,E,F,A);
//Specify inputs and outputs
//See block diagram Fig. 8-10
input S,CLK,Cir;
output E, F;
output [4:1] A;
//Specify system registers
reg [4:1] A; //A register
reg E, F; //E and F flip-flops
reg [1:0] pstate, nstate; //control register
//Encode the states
parameter TO = 2'b00, Tl = 2'b01, T2 = 2'b11;
//State transition for control logic
//See state diagram Fig. 8-11(a)

31. always @(posedge CLK or negedge Clr)
if (~Clr) pstate = TO; //Initial state
else pstate <= nstate; //Clocked operations
(S or A or pstate)
case (pstate)
TO: if (S) nstate = Tl; else nstate = TO;
Tl: if (A[3] & A[4]) nstate = T2; else nstate = Tl;
T2: nstate = TO;
endcase
//Register transfer operations //See list of operation Fig.8-11(b)
(posedge CLK)
TO: if (S)
begin
A <= 4'bOOOO;
F <= 1'bO;
end
Tl:
A <= A + 1'b1;
if (A[3]) E <= 1'bl;
else E <= 1'b0;
T2: F <= I'bl;
endmodule

32. Testing the design description
HDL Example 8-3
//Test bench for design example
module test_design_example;
reg S, CLK, Clr;
wire [4:1] A;
wire E, F;
//Instantiate design example
Example_RTL dsexp (S,CLK.Clr,E,F,A);

33. Example_RTL dsexp (S,CLK.Clr,E,F,A);
initial
begin
Cir = 0;
S = 0;
CLK = 0;
#5 Clr = 1; S = 1;
repeat (32)
#5 CLK = ~ CLK;
end
$monitor("A = %b E = %b F = %b time = %0d". A.E.F,$time);
endmodule