1. An NLTL based Integrated Circuit for a 70-200 GHz VNA System
O. Wohlgemuth, B.Agarwal*, R. Pullela*, D. Mensa*,
Q. Lee*, J. Guthrie*, M. J. W. Rodwell*, R. Reuter,
J. Braunstein, M. Schlechtweg, T. Krems, K. Köhler
Fraunhofer Institute for Applied Solid State Physics (IAF), Tullastr. 72, D Freiburg - Germany
*Department of Electrical and Computer Engineering,
University of California, Santa Barbara, CA 93106
Good morning ladies and gentleman
In my talk I’m introducing a NLTL based integrated circuit for network analysis within GHz.
This work was done at the Fraunhofer Institute for Applied Solid State Physics in Freiburg Germany in collaboration with the University of California in Stanta Barbara.
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2. Outline
Motivation
Conventional S-parameter measurement set-up and integration on a chip
Design and fabrication
Performance of the
integrated components
full chip
Summary
Let me first give a short outline of my talk
After a breif motivation of this work I show a conventional S-parameter measurment set-up and how this can be integrated on a chip
Then I describe the design and fabrication of this integrated circuit.
Several measurements will show the performance of the integrated components and of the full chip.
I will finisch my talk with a short summary
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3. Motivation
Advancement in III-V technology especially in InP based devices
HEMTs and HBTs with fmax > 500 GHz
ICs, operating above 120 GHz
Presently no commercial broadband on-wafer S-parameter measurement system above 120 GHz available
The advancements in III-V technology especially in InP based devices has let to transitors with very high fmax. HEMTs and HBTs attain a fmax of more than 500 GHz.
Also ICs have been introduced which are operating above 120 GHz.
But presently there is no commercial broadband on-wafer S-parameter measurment system above 120 GHz available
But these devices demand a measurment system for characterisation at higher frequencies.
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4. Measurement System Archivierungsangabe
This slilde showes a conventional S-parmeter measurement system.
The RF-source drives a multiplier to generate the high frequency signal which is applied to the DUT. The incident and reflected waves are separated with directional couplers and down converted with sampler or harmonic mixers which are driven from the LO-source. The IF-signals are then measured and evaluated with the HP 8510.
The idea was to integrate all high frequency components on a chip, so no cables or wave guides and connections between the components up to 200 GHz are neccessary. Only the connection to the DUT is neccessary, which can be very short, by packaging the chips into active probes.
Let me show more details of the chip
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5. Block Diagram of the Chip
The stimulus signal drives a NLTL which is used as a frequency multiplier.
The multiplier drives the test port through a dirctional coupler. This coupler operates as a bias tee, and isolates the multiplier from the DC bias applied to the DUT. Further the coupling increases with frequency and reduces the variation of the DUT drive power with frequency. Two additional couplers are integrated to separate the incident an reflected waves and two high speed sampling circuits are used, to convert the signals down to a 20 MHz IF.
The sampling circuits are driven by a second NLTL.
To reduces reflections from the bias connection, a low pass filter is integrated in the bias line.
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6. NLTL Limiting faktors: Bragg Frequency Skin-effect loss and diode loss
Let me now explain the NLTL.
A NLTL is a transmissionline which is periodically loaded with reverse biased diodes. The diodes have a volatge dependant capacitance and form a syntetic line with a voltage dependant velocity of a propagating wave
Near zerro volt, the capacitance of the diodes is high and velocity is slow. At high negativ voltages, the capacitance of the diodes is small and the velocity is fast.
If the input voltage waveform has a negativ going function, the first part of the wave propagate slower as the following parts. So the fall time is becoming shorter and shorter as the wave propagates along the line.
Because the NLTL has a periodic structure it has a Bragg frequency, which limits the fall time together with the skin effect loss and the diode loss.
MD, 26th EuMC 1996

7. Technology Planar Schottky diode process N- layer exponential doped
Further process steps:
Interconnect metal,
Si3N4
Air bridges
The diodes for the NLTL are implemented with Schottkey diodes.
Starting on a semi-insulating GaAs wafer, first a 1mm N+ layer is grown by MBE. An exponential doped N- layer forms the active layer of the diode. For the ohmic contact, the N- layer is etched away. The device area is defined by proton implantation which also defines the resistors. Depositing of the schottky metal form the diodes. Further steps are depositing of the interconnect metal, Siliconnitride for the Capacitores and air bridges for cross overs and airbridge lines.
MD, 26th EuMC 1996

8. Problems with High Drive Frequency
High skin-effect losses
DC walk of because of the high loss
Doides are driven through a minor capacitance variation
Only low power available
Long lines neccassary, to reach enough compression
To use only the 4th harmonics, the NLTL has to bedriven up to 50 GHz.
Problemes with this high drive frequency of occur through the high loss caused by the skin-effect. So the wave is becoming smaller when propagating along the line but the DC-bias is nearly the same. The diodes at the end of the line are not only driven throug a minor capacitance variation but also they are driven through a capacitance region, where the diodes don’t have the strongest capacitance variation.
In addiotion, in this frequency range there aren’t amplifiers with high output power availabel as at lower frequencies and the NLTL has to be longer to reach enough compression.
So it’s very important, to minimize the loss.
MD, 26th EuMC 1996

9. Design of the Multiplier NLTL
Bragg frequency increases exponential
Air bridge line combines wide center conductor with high Bragg frequency
Therefore, there is a special design strategie for the Multiplier NLTL neccasary. At the beginning the NLTL has a wide CPW with low loss but also with a low Bragg frequency. As higher frequencies a generated allong the line, the line becomes smaller and the Bragg frequency increases always so, that the Bragg frequency is not limiting the high frequency generation. At the end of the NLTL, the CPW would become too small, so a air bridge line is used. This combines a wide center conductor with a high Bragg frequency.
In addition, the large signal impedance is changing from 40 to 50 Ohms. So the voltage swing is increasing.
The total line has a length of 4.2mm
Line length: 4.2 mm
MD, 26th EuMC 1996

10. Waveform at the Output of the Multiplier NLTL
Input:
36 GHz sine wave with 12 dBm power
Measured output:
~4.1 ps fall time
This is the measured output voltage waveform of the multiplier NLTL. For this measurment, the NLTL is connected to an on-wafer sampler in a test circuit
The drive power is 12 dBm at 36 GHz.
The measured fall time is 4.1 ps. The real fall time is shorter beacuse of the rise time of the sampler.
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11. Directional Coupler Designed for 180 GHz
10 dB coupling
Zeven, Zodd, geven and godd are calculated with a 3D simulator (HFSS)
For designing the directional couplers, the impedances and complex prapagation constants were calculated with a 3D simulator and choosen for 10 dB coupling. The coulling length was scaled for a center frequency of 180 GHz.
On the right side there is a graph with the measured directivity of this coupler.
For this measurment two test circuits with a NLTL for RF source, a second NLTLwith a high speed sampler for measuring and the coupler are implemented on the wafer.
Measured directivity of the coupler
using on-wafer sampling circuits
MD, 26th EuMC 1996

12. Low Pass Filter
Low pass filter neccassary with low reflection over the entire bandwidth
For designing the low pass filter, it is important, that the reflection is low over the entire bandwith. To attain this, a CPW with elevated center conductor is periodically loaded with Capacitors like a NLTL but with constant capacitors so that the effective line impedance is 50 Ohms. The resistors in serries with the Capacitors cause a attanuation of the line approximately proprtianal to the square of the frequency.
The S-parameter measurement show a small reflection and a moderate attanuation. At 50 GHz the attenuation is 5 dB. With using a external 50GHz biastee, all reflection above 50 GHz from the bias tee and bias connection are attanuated by more than 10 dB, which is sufficient.
ZL=75W
C choosen for Zeff=50W
MD, 26th EuMC 1996

13. Nonlinearity of the Sampling Circuits
Sampling circuit was driven with a input frequency of 36 GHz
Harmonic generation is negligible for input powers below 0 dBm
It is important that the sampler operates in its linear region.
For measuring the nonlinearity of the sampler, one test circuit was driven with a singel 36 GHz input frequency and the output was measured with its harmonics. As the graph showes, harmonic generation is negligible for input powers below 0 dBm.
In the NWA Circuit, the signal gets attenuated by 10 dB through the coupler, so the circuit operates still linear with input signals up to 10 dBm into the test port.
MD, 26th EuMC 1996

14. Power at the DUT Not in the simulation included are:
Attenuation of the sampling circuit
Skin-effect losses of the coupler
GHz is sufficient for measuring
For measuring the power at the DUT one circuit is directly connencted to an on-wafer sampler. The graph on the right side showes the simulated and measured power.
The discrepancy lies in the frequency dependent attanuation of the sampling circuits which is approximately 1 dB at lower frequencies and increases up to estimated 10 dB at 200 GHz. In addition in this simulation the couplers could not be simulated with skin effect losses.
At 200 GHz the signal power is -35 dBm, which is sufficient for a high signal-to-noise ratio at the IF ports.
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15. Measured Directivity of the Full Chip
Measurement of 2 Chips
50 W (44 +/-1.5 W) chip resistor
open test port
This slide showes the measured directivity of the full chip.
The measurement of a circuit with a nominal 50 W chip resistor at the testport is compared to a measurement of another circuit with the open test port.
The directivity is 10 dB, dropping to approximatly 6 dB between 160 to 190 GHz. With a high signal-to-noise ratio, this will be sufficient for calibration up to 200 GHz.
MD, 26th EuMC 1996

16. Summary
The first IC, which can be used as a S-parameter test set within GHz
Design and fabrication
Performance of the single components and the full chip
Packaging these chips into active probes will permit convenient on-wafer S-parameter measurements
Let me summariese the talk:
We have demonstrated the first NLTL based integrated circuit for network analysis within GHz, which can be used as a S-parameter test set for the HP8510.
Further we have shown special aspects for designing an fabricating the IC
Several measurements have described the performance of the components and of the full chip.
Packaging these chips into active probes, which is presently our work, will permit convinient on-wafer S-parameter measurements
This work was supported by the German Ministry BMBF in the frame work of 01BM620 (555339)
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