Instructions: Language of the Computer

Instructions: Language of the Computer
Chapter 2 Sections 2.1 – 2.10 Based on slides from Dr. Iyad F. Jafar

Outline The Von Neumann Architecture Busses & Memory Program Execution
The Computer Language Instruction Set Architecture The MIPS ISA MIPS Design Principles Fallacies and Pitfalls Further Reading More Examples

The Von Neumann Architecture
John Von Neumann,1945 A computer consists of Processor Memory Input and Output Stored-program concept as opposed to program- controlled computers ! Programs and data are loaded into memory prior to execution Different components are connected via set of shared wires called Busses for information exchange Compare to Harvard Architecture! Processor Devices Datapath Input Memory Control Output Stored-program computers were an advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which were programmed by setting switches and inserting patch leads to route data and to control signals between various functional units. In the vast majority of modern computers, the same memory is used for both data and program instructions.

Busses In any computer, there is usually three types of busses Data
Used to exchange data between components Bidirectional Typical size 8, 16, 32, and 64 bits Address Used to specify the source/destination Unidirectional The size of the bus specifies the number of entities (memory locations,I/O) that can be addressed Control Used to specify the operation requested by the CPU (READ, WRITE, and other handshaking operations)

Memory M-1 Data (n bits) Address 2 (Log2 M bits) 1 n bits Control
M-1 Bn-1 B1 B0 Data (n bits) Address (Log2 M bits) 2 Bn-1 B1 B0 1 Bn-1 B1 B0 Bn-1 B1 B0 n bits (Memory Width) Control

Program Execution Program = Instructions + Data
Programs are loaded into memory prior to execution In order to execute the instructions, the CPU Fetches the instruction Read the instruction from memory (Control Unit) Decodes the instruction Understand what should be done (Control Unit) Executes the instruction Perform the required task (Datapath) This is done repeatedly until the end of program ! Fetch Decode Execute

The Computer Language Make it even easier!
Commanding computers requires speaking their language; Binary electric signals at the hardware level (Machine Language) Tedious, time consuming, error-prone, knowledge about processor architecture Make it easier! Represent binary instruction by words (Assembly Language). Convert words to binary manually or using Assemblers One line corresponds to one instruction!! Make it even easier! Make expressing instructions closer to the way humans express operations (High- level Languages) Conversion to machine language is done automatically using Compilers Suppose we want to perform two operations Add two numbers X and Y and store the result in Z Assign element 5 from array ARR to W ADD Z, X, Y READ W, ARR[5] Z = X + Y W = ARR[5]

Instruction Set Architecture
Designing processors requires specifying the type and number of instructions the processor is supposed to support and how a programmer can use it This is specified by the instruction set architecture (ISA) of the processor which includes Instructions (type, encoding, operation …) Memory and I/O access Registers (Why do we need registers !) Different processors have different ISA IA-32, MIPS, SPARC, ARM, DEC, HP, IBM, … The same ISA can be implemented in different ways to achieve different goals Single-cycle, multi-cycle, pipelining, …

Instruction Set Architecture
Generally, the design of ISA could follow one of two schools CISC - Complex Instruction Set Computers RISC - Reduced Instruction Set Computers (~1980s ) CISC RISC Many instructions and addressing modes Few instructions and addressing modes Instructions have different levels of complexity (different size and execution time) Simple instructions of fixed size Shorter programs Longer programs Relatively slow Relatively fast Expensive !!! (not really) Cheaper !! (not really) Intel, AMD, Cyrix MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC RISC The concept was developed by John Cocke of IBM Research during His argument was based upon the notion that a computer uses only 20% of the instructions, making the other 80% superfluous to requirement. A processor based upon this concept would use few instructions, which would require fewer transistors, and make them cheaper to manufacture. By reducing the number of transistors and instructions to only those most frequently used, the computer would get more done in a shorter amount of time. The term 'RISC' (short for Reduced Instruction Set Computer) was later coined by David Patterson, a teacher at the University of California in Berkeley. The RISC concept was used to simplify the design of the IBM PC/XT, and was later used in the IBM RISC System/6000 and Sun Microsystems' SPARC microprocessors. The latter CPU led to the founding of MIPS Technologies, who developed the M.I.P.S. RISC microprocessor (Microprocessor without Interlocked Pipe Stages). Many of the MIPS architects also played an instrumental role in the creation of the Motorola 68000, as used in the first Amigas (MIPS Technologies were later bought by Silicon Graphics).. The MIPS processor has continued development, remaining a popular choice in embedded and low-end market. At one time, it was suspected the Amiga MCC would use this CPU to reduce the cost of manufacture. However, the consumer desktop market is limited, only the PowerPC processor remains popular in the choice of RISC alternatives. This is mainly due to Apple's continuous use of the series for its PowerMac range. CISC CISC (Complex Instruction Set Computer) is a retroactive definition that was introduced to distinguish the design from RISC microprocessors. In contrast to RISC, CISC chips have a large amount of different and complex instruction. The argument for its continued use indicates that the chip designers should make life easier for the programmer by reducing the amount of instructions required to program the CPU. Due to the high cost of memory and storage CISC microprocessors were considered superior due to the requirements for small, fast code. In an age of dwindling memory hard disk prices, code size has become a non-issue (MS Windows, hello?). However, CISC-based systems still cover the vast majority of the consumer desktop market. The majority of these systems are based upon the x86 architecture or a variant. The Amiga, Atari, and pre-1994 Macintosh systems also use a CISC microprocessor. RISC Vs. CISC The argument over which concept is better has been repeated over the past few years. Macintosh owners have elevated the argument to a pseudo religious level in support of their RISC-based God (the PowerPC sits next to the Steve Jobs statue on every Mac altar). Both positions have been blurred by the argument that we have entered a Post-RISC stage. RISC: For and Against RISC supporters argue that it the way of the future, producing faster and cheaper processors - an Apple Mac G3 offers a significant performance advantage over its Intel equivalent. Instructions are executed over 4x faster providing a significant performance boost! However, RISC chips require more lines of code to produce the same results and are increasingly complex. This will increase the size of the application and the amount of overhead required. RISC developers have also failed to remain in competition with CISC alternatives. The Macintosh market has been damaged by several problems that have affected the availability of 500MHz+ PowerPC chips. In contrast, the PC compatible market has stormed ahead and has broken the 1GHz barrier. Despite the speed advantages of the RISC processor, it cannot compete with a CISC CPU that boasts twice the number of clock cycles. CISC: For and Against As discussed above, CISC microprocessors are more expensive to make than their RISC cousins. However, the average Macintosh is more expensive than the WIntel PC. This is caused by one factor that the RISC manufacturers have no influence over - market factors. In particular, the Intel market has become the definition of personal computing, creating a demand from people who have not used a computer previous. The x86 market has been opened by the development of several competing processors, from the likes of AMD, Cyrix, and Intel. This has continually reduced the price of a CPU of many months. In contrast, the PowerPC Macintosh market is dictated by Apple. This reduces the cost of x86 - based microprocessors, while the PowerPC market remains stagnant. Post-RISC As the world enters the 21st century the CISC Vs. RISC arguments have been swept aside by the recognition that neither terms are accurate in their description. The definition of 'Reduced' and 'Complex' instructions has begun to blur, RISC chips have increased in their complexity (compare the PPC 601 to the G4 as an example) and CISC chips have become more efficient. The result are processors that are defined as RISC or CISC only by their ancestry. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the Pentium is a CISC chip, while the 601 is considered to be RISC. CISC chips have also gained techniques associated with RISC processors. Intel describe the Pentium II as a CRISC processor, while AMD use a RISC architecture but remain compatible with the dominant x86 CISC processors. Thus it is no longer important which camp the processor comes from, the emphasis has once-again been placed upon the operating system and the speed that it can execute instructions. EPIC In the aftermath of the CISC-RISC conflict, a new enemy has appeared to threaten the peace. EPIC (Explicitly Parallel Instruction Computing) was developed by Intel for the server market, thought it will undoubtedly appear in desktops over the next few years. The first EPIC processor will be the 64-bit Merced, due for release sometime during 2001 (or 2002, 2003, etc.). The market may be divided between combined CISC-RISC systems in the low-end and EPIC in the high-end. Famous RISC microprocessors 801 To prove that his RISC concept was sound, John Cocke created the 801 prototype microprocessor (1975). It was never marketed but plays a pivotal role in computer history, becoming the first RISC microprocessor. RISC 1 and 2 The first "proper" RISC chips were created at Berkeley University in 1985. ARM One of the most well known RISC developers is Cambridge based Advanced Research Machines (originally Acorn Research Machines). Their ARM and StrongARM chips power the old Acorn Archimedes and the Apple Newton handwriting recognition systems. Since the unbundling of ARM from Acorn, Intel have invested a considerable amount of money in the company and have utilized the technology in their processor design. One of the main advantages for the ARM is the price- it costs less than £10. If Samsung had bought the Amiga in 1994, they would possibly have used the chip to power the low-end Amigas

The MIPS ISA Historical Facts General Features
Microprocessor without Interlocked Pipeline Stages First MIPS processor by John Hennessey in at Stanford University MIPS Technologies, Inc. 1984 First commercial model R General Features RISC 32-bit and 64-bit Register-Register Architecture (Load-Store) ISA revisions  MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64 Different processor models R2000, R3000, R4000, R10000

The MIPS ISA – Register File
5 Read Addr 1 31 B31 B1 B0 5 32 Read Addr 2 Read Data 1 5 Write Addr 32 2 B31 B1 B0 32 Read Data 2 Write Data 1 B31 B1 B0 B31 B1 B0 Read/Write Two read ports for faster access of two operands Can read while writing , dedicated write port 32 bits Inside the CPU SRAM !! Hold data temporarily Some sort of caching of data Why two read ports ?

When writing assembly, these registers can be referenced by their address (number) or name General purpose and special purpose registers # Name Purpose $0 $zero Constant zero $1 $at Reserved for assembler $2 $v0 Function return value $3 $v1 $4 $a0 Function parameter $5 $a1 $6 $a2 $7 $a3 $8 $t0 Temporary – Caller-saved $9 $t1 $10 $t2 $11 $t3 $12 $t4 $13 $t5 $14 $t6 $15 $t7 # Name Purpose $16 $s0 Temporary – Callee-saved $17 $s1 $18 $s2 $19 $s3 $20 $s4 $21 $s5 $22 $s6 $23 $s7 $24 $t8 Temporary – Caller-saved $25 $t9 $26 $k0 Reserved for OS $27 $k1 $28 $gp Global pointer $29 $sp Stack pointer $30 $fp Frame pointer $31 $ra Function return address

There are other registers ! Not directly accessible (no address) PC: Program counter Instruction sequencing LO and HI Used with multiplication and division instructions PC LO HI 32 bits

The MIPS ISA - Instructions
Different categories Arithmetic, logical, memory, flow control All instructions are encoded in binary using 32 bits (Fixed Size!!!) Three different formats depending on the number and type of operands, and operation R-type I-type J-type Instruction encoding Opcode  operation code that specifies the operation in binary Operands  the ins and outs of the instruction

Arithmetic instructions A = B + C ADD A, B, C ADD $s0, $s1, $s2 #$s0 = $s1 + $s2 F = C - A SUB F, C, A SUB $t2, $s6, $s4 #$t2 = $s6 - $s4 Operation Destination, Source1, Source2 destination  source1 op source2 Each arithmetic instruction performs one operation Each instruction has three operands The operands are in the file registers of the datapath The order of operands is fixed

Arithmetic instructions Example 1. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. a = b – c d = 3 * a Solution: assume that the variables a, b, c, and d are associated with registers $s0, $s1, $s2, and $s3, respectively, by the compiler. sub $s0, $s1, $s2 # $s0 contains b – c add $s3, $s0 ,$s0 # $s3 contains 2*a add $s3, $s3, $s0 # $s3 contains 3*a

Arithmetic instructions Example 2. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. f = (g + h) – (i + j) Solution: assume that the variables f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, and $s4, respectively, by the compiler. add $t0, $s1, $s2 # $t0 contains g + h add $t1, $s3 ,$s4 # $t1 contains i + j sub $s0, $t0, $t1 # $s0 contains (g+h) – (i+j) More efficient translation!???

Arithmetic Instructions Machine Language Any instruction has to be encoded using 32 bits including the operation and its operands ADD $t0, $s1, $s4 op rs rt rd shamt funct R-type 6 5 5 5 5 6 op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode

Arithmetic Instructions Machine Language Example 3. What is the machine code for ADD $s0, $t0, $s4 s ADD $s0, $t0, $s4 000000 01000 10100 10000 00000 100000 6 5 5 5 5 6 B H

Arithmetic Instructions Machine Language Example 4. What is the machine code for SUB $s1, $s2, $s3 s SUB $s1, $s2, $s3 000000 10010 10011 10001 00000 100010 6 5 5 5 5 6 B H

Logical Instructions AND, OR, NOR Operation is performed between corresponding bits (bitwise) R-type instruction format Example 5. What is the machine code for AND $s1, $t2, $s2 op = 0x0 rs = $t2 = 0x0A rt = $s2= 0x12 rd = $s1 = 0x11 shamt = 0x00 funct = 0x24 AND $s4, $s3, $t4 # $s4 = $s3 & $t4 OR $s0, $t7, $s3 # $s0 = $t7 | $s3 NOR $s2, $t6, $s3 # $s2 = ~($t6 | $s3) op rs rt rd shamt func 000000 01010 10010 10001 00000 100100

Arithmetic and Logic Instructions with Immediate In many occasions, we encounter high-level statements such as X = Y + 5 Z = W – 4 F = 514 x R If (C>-3) … This implies that the operation is between a register and some constant ! Can we do this with ADD and SUB instructions? Where do these constants come from? MIPS ISA specifies a new set of instructions that deal with immediate data ADDI, ORI, ANDI, XORI, …

Arithmetic and Logic Instructions with Immediate ADDI $t5, $s3, 130 ADDIU $s1, $s2, 15 op rs rt Immediate I-type 6 5 5 16 Immediate Addressing! 16 Sign Extension Instruction 32 Register File Reg[rs] +

Arithmetic and Logic Instructions with Immediate ANDI $t1, $t3, 12 ORI $s3, $a0, 123 op rs rt Immediate I-type 6 5 5 16 Immediate Addressing! 16 Zero Extension Instruction 32 Register File Reg[rs] &

Arithmetic and Logic Instructions with Immediate What if the immediate is greater than 16 bits? In MIPS, this is achieved in two steps using the Load Upper Immediate (LUI) and ORI instructions Suppose we want to add the constant ( )2 to $s0 LUI $t0, # loads the upper 16 bits of $t0 and sets the lower 16 bits to 0 LUI $t0, ( )2 ORI $at, $t0, ( )2

Memory instructions MIPS ISA address bus is 32 bits, i.e. it can address up to 232 (4 G) locations Memory width is usually 8 bits (byte) 0xFF FF FF FF Address Bus (32 bits) MIPS CPU 32-bit Data Bus (32 bits) Read Write 0x 0x 0x 8 bits

Memory instructions Most memories are byte addressable ! Every four consecutive locations (8 bits each) form a word (32 bits) ! In other words, the addresses of two consecutive locations differ by 4 0x E 0x D 0x C 0x B 0x A 0x 0x 0x 0x 0x C 0x 0x 0x 0x 0x 0x 0x 0x C 0x 0x 0x 0x 0x 0x 8 bits 32 bits

Memory instructions Reading from memory requires specifying the address to read from and a register to store the read data Writing to memory requires specifying an address to write to and a register whose content will be written to memory Simple ! However, addressing a memory location requires 32 bits Where do these bits come from ?! Are they stored in memory?! Are they part of the instruction ?! Displacement Addressing In MIPS the address is formed by adding the content of some register (the base register) to 16-bit signed constant (offset or displacement) that is part of the instruction itself. The offset is sign-extended to 32 bits to match the size of the register. A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register Note that the offset can be positive or negative

Memory instructions The Load instruction – reads 32 bit value (A word) into a register lw $t0 , 4 ($s4) Operation Destination Offset Base Register Reg[$t0] = MEM[Reg[$s4]+sign_extend(4)] Memory Data Register File Memory 32 Register Content Address + 32 32 32 16 Sign Extension Instruction offset

Memory instructions The Store instruction – writes the 32 bits (A word) found in a register into a memory location sw $t5 , -12 ($t1) Nemunic Destination Offset Base Register MEM[Reg[$t1]+sign_extend(-12)] = Reg[$t5] Register Content Register File Memory 32 Register Content Address + 32 32 32 16 Sign Extension Instruction offset

Memory instructions The memory is byte-addressable. However, the load and store instructions deal with words (4 bytes)! Reading from memory is effectively reading four bytes! How these bytes are ordered in the 32 bit register ? Storing to memory is storing 32 bits in four consecutive locations. What is the order by which these bits are stored in 4 different locations? Two approaches Little endian: the least significant byte is associated with the location of lowest address (Intel) Big endian: the most significant byte is associated with the lowest address (MIPS)

Reading a word from memory Register Byte 3 Byte 2 Byte 1 Byte 0 0xFD 0x43 0x33 0x10 Little Endian Memory 32 bits 0xFD 0x F5 0x43 0x F4 0x33 0x F3 0x10 0x F2 Register Byte 3 Byte 2 Byte 1 Byte 0 0x10 0x33 0x43 0xFD Big Endian 8 bits 32 bits

Memory Instructions Example 7. Convert the following high-level statements to MIPS assembly language G = 2 * F A[17] = A[16] + G Solution assume that the variables F and G are associated with registers $s4 and $s5, respectively, and the base address of the array A is in $s0. All values are 32-bit integers. add $s5, $s4, $s4 # $s5 contains 2*F lw $t0, 64($s0) # $t0 contains A[16] (note the offset is 64) add $t0, $t0, $s5 # $t0 contains A[16] + G sw $t0, 68($s0) # store $t0 in A[17] (note the offset is 68)

Memory Instructions - Machine Language lw $t0, ($s4) sw $t2, ($at) op rs rt Offset (displacement) I-type 6 5 5 16 The offset is +2^15 -1 or -2^15 op 6-bits opcode that specifies the operation rs 5-bits register file address containing the base address rt 5-bits register file address of destination register (LW) or the source register (SW) Offset 16-bits displacement or offset (number of bytes to move, positive or negative) How far can we move in memory when using LW and SW?

Memory Instructions Example 6 6 bits 5 bits 16 bits Opcode rs rt Offset Machine code for lw $s5, 4($s1) in hexadecimal op = 0x23 rs = $s1 = 0x11 rt = $s5 = 0x15 offset = 0x0004 Machine code for sw $s0, 16($s4) in hexadecimal op = 0x2b rs = $s4 = 0x14 rt = $s0 = 0x10 offset = 0x0010 100011 10001 10101 101011 10100 10000

Memory Instructions MIPS ISA defines memory instructions that can load/store bytes (8 bits) and half words (16 bits) lb $t0, 1($s3) #load byte from memory (sign extention) lbu $t0, 1($s3) #load byte from memory (zeros extension) sb $t0, 6($s3) #store byte to memory lh $t0, 1($s3) #load half word from memory (sign extension) lhu $t0, 1($s3) #load half word from memory (sign extension) sh $t0, 6($s3) #store half word to memory When loading a byte into 32-bit register, where is it stored? Lower 8 bits of the register ! What about remaining bits? When loading a half word into 32-bit register, where is it stored? Lower 16 bits of the register ! What about remaining bits? How about sb and sh instructions?

Memory Instructions LBU $s0, 2 ($s4) # assume Reg[$s4] = 0x F0 Memory Byte 3 Byte 2 Byte 1 Byte 0 0x00 0x00 0x00 0xD0 $s0 0xFD 0x F5 32 bits 0x43 0x F4 0xC3 0x F3 0xD0 0x F2 LB $s0, 2 ($s4) # assume Reg[$s4] = 0x F0 0x30 0x F1 LHU  $s0 = 0x D0 C3 LH  $s0 = 0x FF FF D0 C3 0x04 0x F0 Byte 3 Byte 2 Byte 1 Byte 0 0xFF 0xFF 0xFF 0xD0 $s0 8 bits 32 bits What if the instructions are LH and LHU?

Flow Control Instructions Instructions are loaded in memory! The normal execution of programs is sequential; one instruction after another! Keeping track of execution is done through a special register called the Program Counter (PC) 32 bits (Why???) It is incremented automatically by 4 (why!) after an instruction is fetched Thus, its contents always holds the address of the next instruction! It is not directly accessible !!! (Why) However, in our programs, we often write statements that skip some parts of the program, conditionally or unconditionally !! (IF, SWITCH, WHILE, GOTO … ) How is this implemented in the hardware !? 1) The address bus is 32 bits 2) MIPS instructions are 32bits; each instruction takes four bytes ! 3) The program counter register has no register address!

Flow Control Instructions How to skip instructions in memory to execute others? Basically, this requires using instructions that change the contents of the PC to point to the address where the target instructions are loaded (branch/jump address)! In MIPS, there are no instructions that can modify the PC directly! Alternatively, we have two conditional and three unconditional flow control instructions! These instructions can change the contents of the PC indirectly!

Conditional Flow Control Instructions Branch If Equal Instruction (BEQ) Checks if two registers are equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?). If false, program execution continues normally from the address in PC. This is called PC-relative addressing! Why the offset specifies the number of instructions instead of bytes although the memory is byte addressable? In this way we can skip more instructions (2^15 -1 or -2^15) BEQ $t0 , $t1, 15 Operation Tested Registers Offset

Conditional Flow Control Instructions Branch If Equal Instruction (BEQ) =? Reg1 Reg2 MEM MUX BEQ PC …. Sign Extension Branch Address + …. Address of instruction following BEQ x4 16 bit offset 32 bit instruction from branch address (two registers are equal) Instruction 32 bit instruction next to BEQ (Two registers are not equal)

Conditional Flow Control Instructions Branch If Not Equal Instruction (BNE) Checks if two registers are not equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?)). If false, program execution continues normally from the address in PC. This is called PC-relative addressing! BNE $t0 , $t1, -23 Operation Tested Registers Offset

Flow Control Instructions (Conditional) Branch If Not Equal Instruction (BNE) =? Reg1 Reg2 MEM MUX BNE Branch Address PC …. Sign Extension + …. Address of instruction following BNE x4 16 bit offset 32 bit instruction from branch address (Two registers are not equal) Instruction 32 bit instruction next to BNE (Two registers are equal)

Flow Control Instructions Example 8. Convert the following high-level statements to MIPS assembly language if (x == y) x = x + y end Solution assume that the variables x and y are associated with registers $s4 and $s5, respectively. BNE $s4, $s5, 1 # if $s5 ~= $s4, skip one instruction ADD $s4, $s4, $s # add x and y if they are equal … OR, we can use labels instead of counting how many instructions to skip! BNE $s4, $s5, SKIP # if $s5 ~= $s4, skip one instruction ADD $s4, $s4, $s # add x and y if they are equal SKIP: ….

Flow Control Instructions -Machine Language BEQ $t0, $t1 , BNE $t2, $v1, op rs rt Offset (displacement) I-type 6 5 5 16 We can skip 2^15-1 or -2^15 instructions  2^17-1 or -2^17 bytes op 6-bits opcode that specifies the operation rs 5-bits first register file address to be compared rt 5-bits second register file address to be compared Offset 16-bits displacement or offset (number of instructions to skip, positive or negative!) How many instructions can we skip when using BNE and BEQ?

Conditional Flow Control Instructions Example 9. Machine code for BEQ $s5, $s1, 20 in hexadecimal. op = 0x04 rs = $s5 = 0x15 rt = $s1 = 0x11 offset = 0x0014 Machine code for BNE $s0, $s1, -13 in hexadecimal op = 0x05 rs = $s0 = 0x10 rt = $s1 = 0x11 offset = 0xFFFD 000100 10101 10001 000101 10000 10001

Conditional Flow Control Instructions BEQ and BNE instructions can check for equality only? How about > , < , <= , >= ??? There are no instructions such bgt, bls, bge, ble!! In MIPS ISA, this can be done with the aid of The Set On Less than Instructions (SLT and SLTU) Compares if one register is less than another one If so, a third register is loaded with 1 Otherwise, the third register is loaded with 0 The $Zero register Register number zero Hardwired to zero Can be read only!

Conditional Flow Control Instructions SLT Instruction SLT $s1, $s2, $s3 #set $s1 if $s2 < $s3, else clear $s1 $S1 = 1 Yes $S2 $s2-$s3<0 ?? - $S3 $S1 = 0 No

Conditional Flow Control Instructions SLT Instruction – Machine Language SLT $t0, $s1, $s4 op rs rt rd shamt funct R-type 6 5 5 5 5 6 Opcode for SLT is 0x00 and the func field is 0x2a How about comparing with constants? SLTI How about comparing unsigned numbers? SLTU and SLTIU

Conditional Flow Control Instructions So, how can we execute blt $s1, $s2, L1 ? Such instructions are included in the ISA as pseudo instructions (fake). The assembler takes the job of converting them to actual assembly instructions through using the $at register How about other branch instructions? slt $at, $s1, $s2 bne $at, $zero, L1 ………. L1: blt $s1, $s2, L1 ………. L1:

Unconditional Flow Control Instructions Occasionally, we might need to skip part of the program unconditionally! In MIPS, this is achieved by jump instruction which loads the PC with the 32-bit address of the jump location The 32-bit jump address is formed by Extracting the upper four bits of the PC (Address of next instruction) Appending them to a 26-bit number found in the instruction after multiplying it by 4 (WHY!!!) This is called Pseudo-direct Addressing J label #go to label

Unconditional Flow Control Instructions The Jump Instruction Instruction PC Address Field 26 bits Shift left by 2 4 bits 32 bits 28 bits =

Unconditional Flow Control Instructions The Jump Instruction – Machine Language Opcode 0x02 How far can we move using the jump instruction? What is the machine code for j ? What is the jump addres if the address of the instruction is 0x ? J Label op Address Field J-type 6 26 2^26 instructions within the same frame ! PC<31:28> = 3  we can go to any address between 0x and 0x3F FF FF FC

Branching Far Away ! In programs, branches are local usually! What if we need to skip more than -215 or instructions ! The assembler utilizes the Jump instruction and inverts the condition beq $s0, $s1, L1 ………. L1: bne $s0, $s1, L2 j L1 L2: ………… ………… L1:

Instructions for Accessing Procedures High-level languages support procedures/functions Modularity and code reuse ! Calling a procedure requires Changing the program flow to the place where the procedure is located in memory (branching!!!) Passing arguments ! Storing return values! Returning to the calling program! How is this implemented in the MIPS ISA? Procedure Program Memory

Instructions for Accessing Procedures The Jump and Link (JAL) instruction! This instruction loads the PC with the 32-bit address of the procedure The procedure address is formed in the same way the jump address is formed in the Jump instruction (Pseudo Addressing) Additionally, the instruction saves the contents of the PC in the Return Address register ($ra) ! (WHY!!) JAL ProcedureX Operation Part of the procedure address (26 bits from the instruction)

Instructions for Accessing Procedures The Jump Register (JR) instruction! When the execution of the procedure is finished, it is assumed that the CPU should go back to where it was before invoking the procedure This is done by using the JR instruction Basically, the instruction loads the PC with the contents of some register! In procedures, this register is $ra JR $t0 # Return op rs rt rd shamt funct R-type 6 5 5 5 5 6

Instructions for Accessing Procedures How to pass procedure arguments ? The argument registers ! Registers $a0, $a1, $a2, and $a3 Where to store return values ? The value registers ! Registers $v0 and $v1 What if the procedure uses registers in the caller? What if the procedure calls another one? Temporarily save these registers in memory during procedure execution Retrieve these values upon procedure completion! The STACK !

Instructions for Accessing Procedures The Stack An area of memory used for temporary storage It is a last-in-first out queue Can be accessed like other memory location using Load and Store instructions! However, the base register is a special register called the Stack Pointer ($SP) By convention, the stack grows from high to low address! (WHY!) The SP always points to an occupied location (Top of Stack) Two basic operations on Stack Saving (PUSH)  write data to stack Reading (POP)  read data from stack

Instructions for Accessing Procedures High Address The Stack Push Operation Pop Operation SP ZZ YY $sp = $sp – 4 Store data (word) starting at location pointed by SP! XX New SP WW Low Address High Address New SP ZZ Read data (word) starting at location pointed by SP! SP = SP + 4 YY XX SP WW Low Address

Instructions for Accessing Procedures Example 10. Convert the following code fragment to MIPS assembly (Leaf Procedure) int func1 (int g, h) { int f ; f = (g + h) ; return f ; } Assumptions Argument variables g and h are in argument registers $a0 and $a1, respectively f is assigned to $s0 (need to be saved in stack!) Return value in $v0

Instructions for Accessing Procedures Example 10. func1: addi $sp, $sp, -4 sw $s0, 0($sp) add $s0, $a0, $a1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Push $s0 to stack The procedure Put return value in $v0 Pop $s0 from stack Return

MIPS Design Principles
Simplicity favors regularity Fixed instruction size Few instruction formats Opcode is the first 6 bits Good design demands good compromise Three instruction formats Smaller is faster Limited instruction set Small register file Few addressing modes Make the common case fast Operands are from register file Instructions contain immediate data

Further Reading Non-leaf procedures Translating and Starting a Program
Example in section 2.8 Translating and Starting a Program Section 2.12 The Intel x86 ISA Section 2.17

MIPS Organization So Far
Processor Memory Register File 1…1100 src1 addr src1 data 5 32 src2 addr 32 registers ($zero - $ra) 5 dst addr read/write addr 5 src2 data write data 32 32 32 230 words 32 bits branch offset read data 32 Add PC 32 32 32 32 Add 32 4 write data 0…1100 Fetch PC = PC+4 Decode Execute 32 0…1000 32 4 5 6 7 0…0100 32 ALU 1 2 3 0…0000 32 word address (binary) 32 bits 32 byte address (big Endian)

Review of MIPS Addressing Modes
Register addressing – operand is in a register Base (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction Register relative (indirect) with ($a0) Pseudo-direct with addr($zero) Immediate addressing – operand is a 16-bit constant contained within the instruction op rs rt rd funct Register word operand base register op rs rt offset Memory word or byte operand op rs rt operand

Review of MIPS Addressing Modes
PC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instruction Pseudo-direct addressing – instruction address is the 26- bit constant contained within the instruction concatenated with the upper 4 bits of the PC op rs rt offset Program Counter (PC) Memory branch destination instruction op jump address Program Counter (PC) Memory jump destination instruction =

Fallacies Powerful instruction  higher performance
Fewer instructions required in programming?!?!? But complex instructions are hard to implement! May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code  more errors and less productivity Fallacies  misconception or misbeliefs Pitfall  easily made mistakes

Pitfalls Sequential words are not at sequential addresses
Increment by 4, not by 1 since instructions are 32 bits and memory is word addressable! The offset in branch instructions is the number of instructions It is multiplied in hardware by 4 to convert it to bytes

Reading Assignment Assignment 1. Load-store (register-register) is not the only ISA ! Other ISAs are also available Accumulator Stack Register-Memory Memory-Memory Search the web and read more about these ISAs Assignment 2. Read Section 2.17 – Real Stuff : x86 Instructions

More Examples Example 11. Convert the following high-level code into MIPS assembly language. Make your own association for registers. Assume array to contain signed 32-bit values. A = 5 ; B = 2 * A ; if B < array[12] then array[12] = 0 else array[12] = -20 end

More Examples Example 12. Assume that the following assembly code is loaded in memory. Draw the memory and show its contents assuming that the program counter starts at 0x add $s0, $s1, $s2 beq $s0, $s3, Next lw $s0, -15($s5) Next: lw $s0, 5($s6)

More Examples Example 13. What is the assembly language instruction that corresponds to each of the following machine codes 0x00af8020 0x0c001101

More Examples Example 14. The address of the instruction being executed is 0x , then If this instruction is add $s0, $t9, $zero, then what is the address of the instruction executed after this instruction? If this instruction is j 256, then what is the address of the instruction executed after this instruction? If this instruction is jal 100, then what is the content of the $ra register after executing this instruction? If this instruction is beq $s1, $s2, 25 and the condition evaluates to true, then what is the address of the instruction executed after this instruction?

More Examples Example 15. Convert the following high-level statements into MIPS assembly language. int x ; 32-bit signed number short unsigned int Array[32] ; 16-bit unsigned for (x=0; x=31; x++) { Array[x] = 2 * Array[x] ; }

More Examples Example 16. Convert the following function into MIPS assembly language. Assume that the variable i is in $s0. void strcpy (char x[ ], char y[ ]) { int i ; i = 0 ; while ((x[i] = y[i]) != ‘\0’) i += 1 ; }

Instructions: Language of the Computer

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