1. Introduction to Computer Systems
Lecturer: Steve Maybank
Department of Computer Science and Information Systems
Autumn 2014
Week 6b: Types of Instruction
Official learning outcomes: A knowledge of number systems, computer architectures, data structures, operating systems, algorithms and software engineering fundamentals.
4 November 2014
Birkbeck College, U. London

2. Machine Architecture Main memory Central processing unit Arithmetic/
logic
unit
Address | Cells
Registers 00 1
Program counter
Bus 01 .
Control
unit .
Instruction register FF F
4 November 2014
Brookshear, Section 2.2

3. Machine Language Concepts
Registers (R, S, T…)
Memory addresses
Number of bytes in a memory cell
Instruction
Sequence of instructions
Branching (choice of next instruction)
4 November 2014
Brookshear, Section 2.2

4. Properties of the Illustrative Machine
No. memory cells: 256
No. bits in a memory cell: 8 (1 byte)
No. registers: 16
No. bits in a register: 8 (1 byte)
No. bits in the programme counter: 8 (1 byte)
No. bits in the instruction register: 16 (2 bytes)
4 November 2014
Birkbeck College, U. London

5. Illustrative Machine Language
Op-code
Operand
description 1
RXY
LOAD R from memory location XY 2
LOAD R with data XY 3
STORE R at memory location XY 4
0RS
Move bit pattern in R to S 5
RST
Add (2s comp) contents of S,T. Put result in R 6
Add (fp) contents of S,T.Put result in R
4 November 2014
Brookshear, Appendix C

6. Illustrative Machine Language
Op-code
Operand
Description 7
RST
OR contents of S, T. Put result in R 8
AND contents of S, T. Put result in R 9
XOR contents of S, T. Put result in R A
R0X
Rotate right contents of R for X times. B
RXY
If contents R=contents register 0, then jump to instruction at address XY, otherwise continue as normal. C
000
Halt
4 November 2014
Brookshear, Appendix C

7. Types of Instruction Data transfer LOAD, STORE, MOVE Arithmetic/Logic
ADD, OR, AND, XOR, ROTATE
Control
JUMP, HALT
4 November 2014
Brookshear, Section 2.2

8. Format of an Instruction
Instruction=op-code field+operand field
Op-code: identifies the elementary operation, e.g. STORE, SHIFT, XOR, JUMP.
Operand: additional information, e.g. data or a register address.
4 November 2014
Brookshear, Section 2.2

9. Instruction 156C 1 5 6 C Op-code 1: load Register with bit
pattern in memory
at the given
address
memory address
register
4 November 2014
Brookshear, Section 2.3

10. Op Code 7 (OR) 1 1 1 1st register OR 2nd register = 3rd register
1st register OR 1
2nd register = 1
3rd register
4 November 2014
Brookshear, Section 2.3

11. Op Code A (Rotate right)1
register 1
rotate right 1 1
rotate right 2
4 November 2014
Brookshear, Section 2.3

12. Instruction B258 B 2 5 8 Op-code B: change value of program counter if
contents of indicated
register = contents of
register 0
New contents
of program
counter
Indicated
register
Brookshear, Fig. 2.9.
4 November 2014
Brookshear, Section 2.3

13. Machine Cycle Fetch next instruction from memory to the Decode the CPU
Execute
Execute the
instruction
4 November 2014
Brookshear, Section 2.3

14. First Part of the Fetch Step of the Machine Cycle
Main memory
CPU
address
cells
program counter 15 6C 16 6D A0 A1 A2 A3
bus A0
instruction register
156C
4 November 2014
Brookshear, Section 2.3

15. Completion of the Fetch Step
Main memory
CPU
address
cells
program counter 15 6C 16 6D A0 A1 A2 A3
bus A2
instruction register
156C
4 November 2014
Brookshear, Section 2.3

16. Updating the Program Counter
Fixed length instructions (2 bytes).
Instructions stored consecutively in main memory.
Each memory cell holds 1 byte.
Then pc pc + 2 at the end of each Fetch.
memory
… …
pc=7
4 November 2014
Brookshear, Section 2.3

17. Program to Add Two Values
Get the first value from memory and place it in a register S.
Get the second value from memory and place it in another register T.
Add the contents of S, T and place the result in a register R.
Store the result in R in memory
Stop
4 November 2014
Brookshear, Section 2.3

18. Encoded Program
156C. Load register 5 with the contents of memory cell 6C.
166D. Load register 6 with the contents of memory cell 6D
5056. Add (2s comp) contents of registers 5, 6. Put result in register 0.
306E. Store the contents of Register 0 at memory cell 6E.
C000. Halt.
4 November 2014
Brookshear, Section 2.3

19. Birkbeck College, U. London
Without Instruction B
A program containing n instructions would run for n-1 machine cycles.
The program would be unable to respond to changes in the data.
4 November 2014
Birkbeck College, U. London

20. Birkbeck College, U. London
Fibonacci Numbers
0,1,1,2,3,5,8,13,21,34,55, …
N(1)=0, N(2)=1
N(i+1)=N(i)+N(i-1) for i=2,3,4, …
4 November 2014
Birkbeck College, U. London

21. Program to Find the 10th Fibonacci Number
Address Instruction Comment
// load register 0 with 0
// load register 1 with 0
// load register 2 with 1
// load register 4 with 8
FF // load register 5 with -1 (Two’s Comp) R0 R1 R2 R3 R4 R5 00 00 01 08 ** FF
4 November 2014
Birkbeck College, U. London

22. Program to Find the 10th Fibonacci Number
Address Instruction Comment
2A // Add contents of R1, R2. Put result in R3
3C // Move bit pattern in R2 to R1
2E // Move bit pattern in R3 to R2
// Add contents of R4, R5. Put result in R4
B436 // If contents R4=contents R0, go to 36
B02A // If contents R0=contents R0, go to 2A
C000 // Halt. Result is in R2.
4 November 2014
Birkbeck College, U. London

23. Assembly Language Mnemonic system for representing machine language
166D
5056
306E
C000
Assembly language
LD R5, Price
LD R6, ShippingCharge
ADDI R0, R5, R6
St R0, TotalCost
HLT
4 November 2014
Brookshear, Section 6.1