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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 1 Bruce Mayer, PE Engineering-45: Materials of Engineering Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 45 PhotoLithography MOSFET Fab
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 2 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning - 1 Begin with a precise flat surface such as silicon wafer silicon substrate
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 3 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning - 2 A THIN layer of a different material is deposited or grown on the substrate silicon substrate oxide field oxide
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 4 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning - 3 A Thin layer of PHOTOsensitive, and acid/etch chemical RESISTING material (a.k.a. PhotoResist) is applied to the wafer silicon substrate oxide photoresist
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 5 Bruce Mayer, PE Engineering-45: Materials of Engineering Shadow on photoresist photoresist Exposed area of photoresist Chrome plated glass mask Ultraviolet Light silicon substrate oxide Litho-4: Ultraviolet light Exposes photoresist through windows in a photomask
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 6 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning – 5 Exposed photoresist becomes soluble and can be easily removed by a “developer” chemical. Unexposed area of photoresist silicon substrate Exposed area of photoresistoxide photoresist
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 7 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning – 6 Unexposed photoresist remains on surface of oxide to serve as a temporary protective mask for areas of the oxide that are not to be etched/disolved silicon substrate oxide photoresist photoresist
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 8 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning – 7 Areas of oxide protected by photoresist remain on the silicon substrate while exposed oxide is removed by the etching process. silicon substrate oxide oxide photoresist
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 9 Bruce Mayer, PE Engineering-45: Materials of Engineering PhotoLithoGraphic Patterning – 8 The photoresist is removed using a “stripping process” -- revealing the patterned “window” on the thin oxide layer. silicon substrate oxide oxide Oxide Layer
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 10 Bruce Mayer, PE Engineering-45: Materials of Engineering Intel squeezes 2 BILLION transistors onto new Itanium chip – Feb08 The new 65-nanometer Tukwila Itanium processor, which is expected to be released at the end of 2009, will run at up to 2 GHz, have dual-integrated memory controllers and use Intel's QuickPath interconnect instead of a front-side bus. The processor also will have 2 billion transistors on one chip BUT...What is a TRANSISTOR? What KIND of Transistors are used? HOW are the Transistors MADE?
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 11 Bruce Mayer, PE Engineering-45: Materials of Engineering Acknowledgement These Following Images Were Graciously Provided by Michael W. Davidson National High Magnetic Field Laboratory 1800 E. Paul Dirac Dr. The Florida State University Tallahassee, Florida 32310 Tel: 850-644-0542 Fax: 850-644-8920 email: davidson@magnet.fsu.edu web: http://microscopy.fsu.edu
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 12 Bruce Mayer, PE Engineering-45: Materials of Engineering n-MOSFET Electronic Device negative channel, Metal-Oxide-Silicon, Field-Effect Transfer-resistor (Transistor) Source Drain Gate Drain Electrical Current VgVg VdVd VsVs d s g
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 13 Bruce Mayer, PE Engineering-45: Materials of Engineering 1. Form Gate & Isolation Dielectric Oxidize P-Type Silicon in Tube Furnace 1000-1100 °C in O 2 or Wafer-Vapor Forms Insulating Layer of Silicon Dioxide (SiO 2 ) –Yellow Layer Below
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 14 Bruce Mayer, PE Engineering-45: Materials of Engineering 2. Apply Photo Resist Spin on “Thick” Liquid Photo Resist (blue) and “Soft- Bake” to make resist plastic-like
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 15 Bruce Mayer, PE Engineering-45: Materials of Engineering 3. Expose the Negative PhotoResist First Mask Placed Over PhotoResist UltraViolet Light Projected onto the Mask Exposed PhotoResist Hardens (negative resist)
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 16 Bruce Mayer, PE Engineering-45: Materials of Engineering 4. Develop Exposed PhotoResist Unexposed (and soft) PhotoResist (PR) is Washed away by the “Developer” Solution Leaves the exposed PR and SiO 2 in tact
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 17 Bruce Mayer, PE Engineering-45: Materials of Engineering 5. Etch SiO 2 to form Gate Dielectric Etch the Thin the SiO 2 Using “Plasma Etching” Leave only a Very Thin Insulating Layer
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 18 Bruce Mayer, PE Engineering-45: Materials of Engineering 6. Remove Used PhotoResist Hardened PhotoResist is removed by one of: Liquid Solvent Gaseous Ozone “Ashing”
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 19 Bruce Mayer, PE Engineering-45: Materials of Engineering 7. Deposit Gate Electrode Film Deposit a Layer of Polycrystalline Silicon (red) by Low Pressure Chemical Vapor Deposition (LPCVD)
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 20 Bruce Mayer, PE Engineering-45: Materials of Engineering 8. Apply 2 nd Layer of PhotoResist Cover PolySi with PhotoResist in Preparation for the Next Mask Step
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 21 Bruce Mayer, PE Engineering-45: Materials of Engineering 9. Expose PhotoResist Using Mask-2 The 2 nd Mask is placed Over the PR PR exposed to UV Light
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 22 Bruce Mayer, PE Engineering-45: Materials of Engineering 10. Develop Gate Electrode PR Use the Developer to Wash Away UnWanted PR Leave Behind a “T” shaped PR pattern
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 23 Bruce Mayer, PE Engineering-45: Materials of Engineering 11. Pattern Gate PolySilicon Use “Dry” Plasma Etching Techniques to Remove BOTH PolySi and SiO 2 in areas Not Protected by PR
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 24 Bruce Mayer, PE Engineering-45: Materials of Engineering 12. Remove PR to Complete Gate Electrode Remove PR by Ozone Ashing Leaves a Strip of PolySi which Rises Above the Exposed Silicon
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 25 Bruce Mayer, PE Engineering-45: Materials of Engineering 13. Change Exposed Si from P-type to N-type Ion-Implant Phosphorus or Arsenic to Convert the Exposed Silicon to N-Type
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 26 Bruce Mayer, PE Engineering-45: Materials of Engineering 14. Deposit Electrical Contact Insulation Deposit SiO 2 by TEOS+O 3 APCVD The SiO 2 may P or P+B doped
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 27 Bruce Mayer, PE Engineering-45: Materials of Engineering 15. Apply Contact Via PR Apply a 3 rd Layer of PhotoResist that Will be used to Form the Vertical Shafts used for Electrical Contacts
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 28 Bruce Mayer, PE Engineering-45: Materials of Engineering 16. Expose PR using 3 rd Mask Again Exposed Masked PR to UV Light The Black Rectangles Will Define the Contact Holes
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 29 Bruce Mayer, PE Engineering-45: Materials of Engineering 17. Develop Contact-Via PR Develop the PR to Expose the SiO 2 in the desired Contract areas
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 30 Bruce Mayer, PE Engineering-45: Materials of Engineering 18. Expose Silicon Thru Etching Etch the SiO 2 Not Protected by the PR to Expose the underlying Silicon PolySi at rear N-Type Si at Front-Left & Front-Right
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 31 Bruce Mayer, PE Engineering-45: Materials of Engineering 19. Remove Contact-Via PR Remove the PR to Reveal Contact holes, or vias, in the insulating APCVD-SiO 2
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 32 Bruce Mayer, PE Engineering-45: Materials of Engineering 20. Deposit Aluminum Contact Wiring Blanket Deposit Al-Cu Alloy by Sputtering Al Contacts the Si and PolySi thru the holes in the APCVD-SiO 2
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 33 Bruce Mayer, PE Engineering-45: Materials of Engineering 21. Apply “Wiring” PhotoResist Apply a 4 th Layer of PhotoResist that Will be used to Form the Al-Cu “wires” that Carry Electrical Current and Potential (Voltage) to the Transistor
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 34 Bruce Mayer, PE Engineering-45: Materials of Engineering 22. Metallization Exposure Expose the PR using the Metallization Mask
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 35 Bruce Mayer, PE Engineering-45: Materials of Engineering 23. Develop Metallization PR Develop PR Exposing Regions of the Al-Cu Metal for Subsequent Removal
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 36 Bruce Mayer, PE Engineering-45: Materials of Engineering 24. Etch UnProtected Al-Cu to Form “Wires” The Final Etching Step Removes the Unwanted Metal; Leaving only Metal used for Contacting thru the Vertical-Shaft Vias the Silicon Source/Drain and Poly-Si Gate Forming Strips of Al-Cu that act as Wires
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BMayer@ChabotCollege.edu ENGR-45_Lec-06_Diffusion_Fick-1.ppt 37 Bruce Mayer, PE Engineering-45: Materials of Engineering 25. Remove Remaining Resist Xsistor Done Remove the Remaining Metallization Resist, Completing the n-MOSFET Transistor Millions of transistors can be formed Simultaneously
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