2. CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava 1/15/20151 Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

3. CML CMLAnnouncements Important announcements will be made at the beginning of the lecture Blackboard is setup –If you cannot access, let me know immediately –Make it an interactive forum Lectures –Will be fast paced, so read before and after the class –Stop me as soon as you have a question, or you do not understand. Realize that it is your last chance Learning is your prerogative –I will skip some things that are in the textbook, and will teach somethings that are not in the textbook Now you are in college 1/15/20152

4. CML CML More Announcements Green card in front of the book –Take out half an hour to browse through it MARS – MIPS Simulator –Write programs in MIPS assembly language –Is needed for projects 1 and 2 –Start playing with MARS Quiz will be 45 mins –open book and notes –One question will be difficult Quiz 1 –Thursday Sept 10, 2009. –Arithmetic, Load/Store and Branch Instructions 1/15/20153

5. CML CML The Instruction Set Architecture (ISA) 1/15/20154 instruction set architecture software hardware ISA - The interface description separating the software and hardware.

6. CML CML Below the Program 1/15/20155 High-level language program (in C) swap (int v[], int k)... Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 C - Compiler Assembler

7. CML CML Higher-Level Languages Higher-level languages –Allow the programmer to think in a more natural language Customized for their intended use, e.g., –Fortran for scientific computation –Cobol for business programming –Lisp for symbol manipulation –Improve programmer productivity and maintainability more understandable code that is easier to debug and validate –Independent of Computer on which it applications are developed Computer on which it applications will execute Enabler –Optimizing Compiler Technology Very little programming at the assembler level 1/15/20156

8. CML CML MIPS R3000 Instruction Set Architecture Instruction Categories –Arithmetic –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special 1/15/20157 R0 - R31 PC HI LO OP rsrt rdsafunct rs rtimmediate jump target 3 Instruction Formats: all 32 bits wide Registers

9. CML CML RISC Vs. CISC MIPS ISA is a RISC ISA RISC – Reduced Instruction Set Computer CISC – Complex Instruction Set Computer Many differences –Will learn over the lectures One main difference –In MIPS (a RISC architecture), all instructions are 32-bits –In IA32 (a CISC architecture), instructions can be of variable widths 1/15/20158

10. CML CML MIPS ISA: Arithmetic Instructions MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands destination  source1 op source2 All operands are contained in the Register File –$t0, $s1,$s2 are in Register File Operand order is fixed 1/15/20159

11. CML CML Compiling More Complex Statements What is the assembler equivalent of h = (b - c) + d Assume –Variable b is stored in register $s1 –Variable c is stored in $s2 –Variable d is stored in $s3 –Result is to be left in $s0 1/15/201510 sub$t0, $s1, $s2 add$s0, $t0, $s3 ## $t0 = b - c ## $s0 = $t0 + d

12. CML CML MIPS Register File All source operands of arithmetic instructions must be from the Register File All the destination operands of arithmetic instructions must be written into the Register File Register File –Holds thirty-two 32-bit registers –Two read ports and –One write port Registers are –Faster than main memory –Easier for a compiler to use e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack –Can hold variables so that code density improves (since register are named with fewer bits than a memory location) Register addresses are indicated by using $ 1/15/201511 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations 32 5 5 5

13. CML CML Register Naming Convention 1/15/201512 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hardware) 0$zero constant 0 (Hardware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7

14. CML CML MIPS ALU 32-bit ALU –2 32-bit sources –1 32-bit result Operations –Arithmetic ADD, SUB,... –Logical AND, OR, NOR, XOR, … 1/15/201513 ALU 32-bit

15. CML CML How does it work? sub$t0, $s1, $s2 1/15/201514 Register File src1 reg no src2 reg no src1 data src2 data $t0  R8 $s1  R17 $s2  R18 R0 R1 R8 25 R17 R18 17 18 10 25 10 - dst addr write data 15 8 R31 25 10 Arithmetic instructions can only change the contents of the Register File –In CISC processors, arithmetic instructions are much more powerful – they can read and change the contents of the memory

16. CML CML MIPS R3000 Instruction Set Architecture Instruction Categories –Arithmetic –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special 1/15/201515 R0 - R31 PC HI LO OP rsrt rdsafunct rs rtimmediate jump target  3 Instruction Formats: all 32 bits wide Registers

17. CML CML Memory Arithmetic instructions operands must be registers –How do we get data into and out of memory? Remember, program and data reside in memory (Not in registers) –What about programs with a lot of variables? 1/15/201516 Processor Control Datapath Memory Devices Input Output

18. CML CML Accessing Memory MIPS has two basic data transfer instructions for accessing memory lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory (assume $s3 holds 24 10 ) The data transfer instruction must specify –Memory address where in memory to read from (load) or write to (store) –Register destination (source) where in the register file to write to (load) or read from (store) The memory address is formed by –summing the constant portion of the instruction and the contents of the second register 1/15/201517 28 32

19. CML CML Processor – Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array 1/15/201518 Processor Memory ? locations read addr/ write addr read data write data 32 2 32 ? width

20. CML CML Memory Organization How wide is the memory What is each unit Each unit is a bit –0, 1 8-bits = 1 byte –In MIPS memory is byte addressable –2 32 locations of 1 byte Software likes to operate on “words” –1 word = 4 bytes = 32 bits –2 30 locations of 1 word 1/15/201519 Memory 2 32 Locations 8-bit 32-bit 2 30 Locations

21. CML CML MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? 1/15/201520 Memory... 0 1 0 0 DataWord Address 0 4 8 12 16 20 24... 1 0 0 0... 0 0 1 0... 0 0 0 1... 1 1 0 0... 0 1 0 1... 0 1 1 0 $s3 holds 8 in location 16... 0001

22. CML CML Compiling with Loads and Stores Assume –Variable b is stored in $s2 –Base address of array A is in $s3 What is the MIPS assembly code for A[8] = A[2] - b 1/15/201521 $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0] lw$t0, 8($s3) sub$t0, $t0, $s2 sw$t0, 32($s3)

23. CML CML Compiling with a Variable Array Index Assume –A is an array of 50 elements –Base of A is in register $s4 –Variables b, c, and i are in $s1, $s2, and $s3 What is the MIPS assembly code for c = A[i] - b 1/15/201522 add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i add$t1, $t1, $s4#addr of A[i] lw$t0, 0($t1) sub$s2, $t0, $s1

24. CML CML Assembly Generation: Arithmetic Instructions Instructions, like registers and words of data, are also 32 bits long –Example: add $t0, $s1, $s2 –registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: 1/15/201523 op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 What do the field names stand for?

25. CML CML MIPS Instruction Fields op rs rt rd shamt funct 1/15/201524 op rs rt rd shamt funct 6 bits5 bits 6 bits = 32 bits opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field R Format

26. CML CML Assembly Generation: Load Instruction Consider the load-word and store-word instructions, –What would the regularity principle have us do? –New principle: Good design demands a compromise Introduce a new type of instruction format –I-type for data transfer instructions –previous format was R-type for register Example: lw $t0, 24($s2) 1/15/201525 op rs rt 16 bit number 100011 10010 01000 0000000000011000 35 18 8 24 I Format

27. CML CML Assembly Generation: Store Instruction sw $t0, 24($s2) 1/15/201526 op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000 A 16-bit address means access is limited to memory locations within a region of  2 13 or 8,192 words (  2 15 or 32,768 bytes) of the address in the base register $s2

28. CML CML Assembling Code Example: A[8] = A[2] – b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS code for these three instructions 1/15/201527 35 lw 1988 43 sw 19832 0 sub 8188034

29. CML CML MIPS Data Types 1/15/201528 Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Integers: Unsigned Integers Signed Integers - 2's complement Floating Point

30. CML CML Decimal, Hexadecimal, and Binary 1/15/201529 00 0 0000 01 1 0001 02 2 0010 03 3 0011 04 4 0100 05 5 0101 06 6 0110 07 7 0111 08 8 1000 09 9 1001 10 A 1010 11 B 1011 12 C 1100 13 D 1101 14 E 1110 15 F 1111 1010 1100 0011 (binary) = 0xAC3 10111 (binary) = 0001 0111 (binary) = 0x17 0x3F9 = 11 1111 1001 (binary) MEMORIZE!

31. CML Unsigned Binary Representation HexBinaryDecimal 0x000000000…00000 0x000000010…00011 0x000000020…00102 0x000000030…00113 0x000000040…01004 0x000000050…01015 0x000000060…01106 0x000000070…01117 0x000000080…10008 0x000000090…10019 … 0xFFFFFFFC1…11002 32 -4 0xFFFFFFFD1…11012 32 -3 0xFFFFFFFE1…11102 32 -2 0xFFFFFFFF1…11112 32 -1 1/15/201530

32. CML Signed Binary Representation : 2’s C binarydecimal 1000-8 1001-7 1010-6 1011-5 1100-4 1101-3 1110-2 1111 00000 00011 00102 00113 01004 01015 01106 01117 1/15/201531 2 3 - 1 = -(2 3 - 1) = -2 3 = 1010 complement all the bits 1011 and add a 1

33. CML CML Memory Address Location lw $t0, 24($s2) 24 10 + $s2 = 1/15/201532 Memory dataword address (hex) 0x00000000 0x00000004 0x00000008 0x0000000c 0xf f f f f f f f $s2 0x12004094 0x00000002 Note that the offset can be positive or negative... 1001 0100 +... 0001 1000... 1010 1100 = 0x120040ac

34. CML MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1 1/15/201533

35. CML CML Review: MIPS R3000 ISA Instruction Categories –Arithmetic –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special 1/15/201534 R0 - R31 PC HI LO OP rsrt rdsafunct rs rtimmediate jump target Registers R Format I Format 6 bits5 bits 6 bits 3 Instruction Formats: all 32 bits wide 6 bits5 bits 6 bits

36. CML CML Review: MIPS Organization so far Arithmetic instructions – to/from the register file Load/store instructions - to/from memory 1/15/201535 32 registers ($zero - $ra) read data 32 5 5 5 src1 addr src2 addr dst addr write data 32 bits 32 Processor Memory 32 bits 2 30 words read/write addr write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 data src2 data 32 ALU 0123 7654 byte address (big Endian)

37. CML CML Review: Naming Convention for Registers 1/15/201536 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hardware) 0$zero constant 0 (Hardware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7

38. CML CML MIPS Data Types 1/15/201537 Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Integers: Unsigned Integers Signed Integers - 2's complement Floating Point

39. CML CML Yoda says… Named must your fear be before banish it you can 1/15/201538