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EDA Lab. Dept. of Computer Engineering C. N. U. 1 FSM Structures Mealy, Moore and Combined Mealy/Moore outputs Figure 8.3

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EDA Lab. Dept. of Computer Engineering C. N. U. 2

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3 Bad FSM Model State Diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 4 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 5 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 6 Problems of FSM1 – BAD 1.no reset, no next state value defined for the unused state. –2bits FFs: 3 states used, one unused state. 2.Read and Write output assignment infer extra two FFs. –To avoid extra FFs, use separate combinational process. 3.variable initialization –Ignored by the synthesis tools.

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EDA Lab. Dept. of Computer Engineering C. N. U. 7 FSM1_GOOD

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EDA Lab. Dept. of Computer Engineering C. N. U. 8

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9 Synthesized Circuit

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EDA Lab. Dept. of Computer Engineering C. N. U. 10 FSM 2 State Diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 11 VHDL Code (Bad)

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EDA Lab. Dept. of Computer Engineering C. N. U. 12 Contd Output Y –Assigned under clockevent … statement. –Extra FFs are inferred.

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EDA Lab. Dept. of Computer Engineering C. N. U. 13 Good Model 1 (1 sequential process, 1 combination process, selected signal assignment for Y)

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EDA Lab. Dept. of Computer Engineering C. N. U. 14 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 15 Sequential process & Combinational process Sequential process –Description with respect to the edge point –Input sampled just before the edge –Output Combinational process inputoutput inputoutput

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EDA Lab. Dept. of Computer Engineering C. N. U. 16 FSM 2_GOOD2 Combined current state and next state logic Separate output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 17 Separate output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 18 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 19 Synthesized Circuit

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EDA Lab. Dept. of Computer Engineering C. N. U. 20 FSM 2_GOOD3 Combined next state and output logic Separate current state logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 21 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 22

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EDA Lab. Dept. of Computer Engineering C. N. U. 23 FSM 2_GOOD4 Combined current state, next state and output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 24 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 25

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EDA Lab. Dept. of Computer Engineering C. N. U. 26 Car Speed Controller FSM State Diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 27 Input primary branch directives

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EDA Lab. Dept. of Computer Engineering C. N. U. 28

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EDA Lab. Dept. of Computer Engineering C. N. U. 29 State value primary branch directives

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EDA Lab. Dept. of Computer Engineering C. N. U. 30

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EDA Lab. Dept. of Computer Engineering C. N. U. 31 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 32 Angular Position FSM using Gray and Johnson state encoding State Diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 33 Contd Input –Physical Position: asynchronous input(loaded when reset = 1) –MOVE CW: 45˚ clock wise move –MOVE CCW: 45˚ counter clock wise move Two ways of representing state encoding 1.Use a signal of an enumerated type for which a single synthesis specific attribute is applied. Attribute name is specific to the synthesis tool, not portable, needs to be changed.

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EDA Lab. Dept. of Computer Engineering C. N. U. 34 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 35 Contd 2. Use constants to represent the individual state values. It is directly portable to other synthesis tools.

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EDA Lab. Dept. of Computer Engineering C. N. U. 36

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EDA Lab. Dept. of Computer Engineering C. N. U. 37 Angular position FSM

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EDA Lab. Dept. of Computer Engineering C. N. U. 38 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 39 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 40 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 41 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 42 Black Jack Game Machine Blackjack Game –Blackjack is the most popular of the card games played at the tables in casinos. It is played with a standard deck of 52 cards. The four suits; spades, hearts, diamonds and clubs have no significance and are ignored. The Jack, Queen and King all have a value of 10. The ace is the most powerful card having a value of 1 or 11 depending upon what the player chooses. –Blackjack is also known as pontoon or 21 because 21 is the highest rated total card value a player can hold. Blackjack is the name given to the strongest hand consisting of an ace and a 10 valued card. –The object of the game is to beat the dealer. The dealer has no object other than to follow the rules of the casino, which is to stand(hold) on hands of 17 or more, and to draw another card on hands of 16 or less. –A player looses if his or her total card value is less than the dealers total, or, he or she has over 21 and so has bust. If a player wants to improve his hand he can ask the dealer for another card. This is called drawing or hitting. If satisfied with the total card value he can stand(hold).

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EDA Lab. Dept. of Computer Engineering C. N. U. 43

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EDA Lab. Dept. of Computer Engineering C. N. U. 44

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EDA Lab. Dept. of Computer Engineering C. N. U. 45

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EDA Lab. Dept. of Computer Engineering C. N. U. 46 VHDL package defining four enumerated state encoding data types

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EDA Lab. Dept. of Computer Engineering C. N. U. 47

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EDA Lab. Dept. of Computer Engineering C. N. U. 48 FSM with selectable state encoding – Blackjack game machine

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EDA Lab. Dept. of Computer Engineering C. N. U. 49 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 50 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 51 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 52 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 53 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 54 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 55 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 56 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 57 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 58 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 59 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 60 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 61 FSMs with a Mealy or Moore output State Diagram for FSMs with a Mealy and Moore output

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EDA Lab. Dept. of Computer Engineering C. N. U. 62

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EDA Lab. Dept. of Computer Engineering C. N. U. 63 FSM modeled with NewColor as a Mealy type output

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EDA Lab. Dept. of Computer Engineering C. N. U. 64 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 65 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 66 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 67 FSM modeled with NewColor as a Moore type output

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EDA Lab. Dept. of Computer Engineering C. N. U. 68 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 69 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 70 FSM modeled with a Mealy and a Moore Output

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EDA Lab. Dept. of Computer Engineering C. N. U. 71 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 72 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 73 Contd Moore Output –Dependent only on the current state, early output.

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EDA Lab. Dept. of Computer Engineering C. N. U. 74 FSM with sequential next state logic Extra FF in the next state logic. State Diagram –BeenlnState3B (extra FF)

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EDA Lab. Dept. of Computer Engineering C. N. U. 75

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EDA Lab. Dept. of Computer Engineering C. N. U. 76 FSM with sequential next state logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 77 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 78 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 79 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 80 Contd Inferred FSM Structure with an additional FF in the next state logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 81 FSM with sequential output logic –State machine with an embedded counter Counter: parts of the state machines output logic. –State diagram implying sequential output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 82 State diagram implying sequential output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 83 FSM with sequential output logic

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EDA Lab. Dept. of Computer Engineering C. N. U. 84 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 85 Contd Tried to use a synchronized value

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EDA Lab. Dept. of Computer Engineering C. N. U. 86 Inferred FSM Structure with embedded counter

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EDA Lab. Dept. of Computer Engineering C. N. U. 87 FSM with sequential next state and output logic - Blackjack Figure 8.12 State Diagram –VHDL coded with one single process statement.

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EDA Lab. Dept. of Computer Engineering C. N. U. 88 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 89 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 90 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 91 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 92 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 93 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 94 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 95 Interactive State Machine 1.Unidirectional

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EDA Lab. Dept. of Computer Engineering C. N. U. 96

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EDA Lab. Dept. of Computer Engineering C. N. U. 97 Interactive State Machine 2. Bidirectional

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EDA Lab. Dept. of Computer Engineering C. N. U. 98

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EDA Lab. Dept. of Computer Engineering C. N. U. 99 Unidirectional interactive FSMs Three different ways of controlling data path with unidirectional interactive FSMs

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EDA Lab. Dept. of Computer Engineering C. N. U. 100

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EDA Lab. Dept. of Computer Engineering C. N. U. 101 Data Path –Accepts three or four 4-bits values on the input. –Processes them, to provide sequences of either two or three, 9-bits values on the output. –Input data: A, B, C, D –Output data: Y1, Y2, Y3, (Y4) When ThreeOnly = 0 Y1 = A.B + A.C Y2 = A.D + B.C Y3 = B.D + C.D When ThreeOnly = 1 Y1 = A.B + A.C Y4 = B.C –Data Path controlled from Control Path 1, 2, 3

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EDA Lab. Dept. of Computer Engineering C. N. U. 102

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EDA Lab. Dept. of Computer Engineering C. N. U. 103 Control Path 1 Control Path –FSM master send Start FSM1, Start FSM2, Start FSM3 –FSM 1 Dedicated to provide four enable signals used to clock the serial input data into the appropriate holding register. –FSM 2 Send select signals which of the two held inputs to multiply together. Provide enable signals used to clock the multiplied result into the appropriate state register. –FSM 3 Simply provide the select lines used to select which result to output.

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EDA Lab. Dept. of Computer Engineering C. N. U. 104 Contd Control Signals in control path 1

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EDA Lab. Dept. of Computer Engineering C. N. U. 105 Contd Master FSM state diagram and FSM1, FSM2, FSM3 state diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 106 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 107 Control Path 2 Three state diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 108 Contd Control Path state diagram

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EDA Lab. Dept. of Computer Engineering C. N. U. 109 1. Data path(VHDL Code)

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EDA Lab. Dept. of Computer Engineering C. N. U. 110 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 111 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 112 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 113 2. Control Path 1 (VHDL Code)

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EDA Lab. Dept. of Computer Engineering C. N. U. 114 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 115 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 116 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 117 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 118 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 119 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 120 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 121 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 122 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 123 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 124 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 125 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 126 3. Control Path 2 (VHDL Code)

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EDA Lab. Dept. of Computer Engineering C. N. U. 127 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 128 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 129 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 130 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 131 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 132 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 133 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 134 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 135 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 136 4. Control Path 3 (VHDL Code)

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EDA Lab. Dept. of Computer Engineering C. N. U. 137 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 138 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 139 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 140 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 141 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 142 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 143 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 144 Two Interactive FSM Controlling rotors –To control two mechanical interlocking rotors, which rotate in 90˚ increments in a clockwise or counter clockwise.

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EDA Lab. Dept. of Computer Engineering C. N. U. 145

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EDA Lab. Dept. of Computer Engineering C. N. U. 146 Contd Two Interactive FSM Controlling rotors –FSM1(FSM2) controls the rotor R1(R2) –Four states(Ang0, Ang90, Ang180, Ang270) –Inputs: CW-R1, CCW-R1, CW-R2, CCW-R2 –Two rotors should not be in the same position –Primary drive, Secondary drive Cannot be in or moved to some where if it is not occupied by the primary drive –R1_R2b = 1: R1 is drive R1_R2b = 0: R2 is drive

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EDA Lab. Dept. of Computer Engineering C. N. U. 147

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EDA Lab. Dept. of Computer Engineering C. N. U. 148 VHDL Code

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EDA Lab. Dept. of Computer Engineering C. N. U. 149 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 150 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 151 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 152 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 153 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 154 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 155 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 156 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 157 Contd

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EDA Lab. Dept. of Computer Engineering C. N. U. 158 Contd

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