Presentation on theme: "V6 GTX Gu Yongguo Note: this draft has HXT and Fujisan content removed because it will be given to reps and external-to-xilinx. To engage customers on."— Presentation transcript:
1 V6 GTXGu YongguoNote: this draft has HXT and Fujisan content removed because it will be given to reps and external-to-xilinx. To engage customers on this material, please contact Panch Chandrasekaran or Anthony Torza.
7 Transceiver Overview Virtex-6 Transceivers - GTX Available in Virtex-6 LXT, SXT and HXTRange: 480 Mbps – 6.5 GbpsCompliant to major protocol standardsGigabit Ethernet, PCI Express Gen1 & Gen2, OC-48, XAUI, HD-SDI, OBSAI, CPRI, SRIO, FC-1/2/4, Interlaken, CEI-6OOB signaling for PCI ExpressBuilt-in Linear EQ, DFE and Tx Pre-emphasisHighly flexible clockingIndependent PLLs for TX and RXPower dissipation: < 150 mW typ
8 Reference Clock Easier than it looks Intelligent Pin SelectionConnect IBUFDS_E1 to MGTREFCLKTX/RXWizard will sort this out for you!The wizard selections will make the correct connectionsIncludes north and south bound routesAdvanced Users:Can use MUX connections to specify specific clock routesComplex view available to assist in Clock Switching applications2 Refclks (RefClk0 and 1)from pins(Like Virtex-5)2 Refclks cascadefrom NorthQuadPERFCLK andGREFCLKFrom Fabric2 Refclks cascadefrom SouthQuad
14 Reference clock connection Single Clock Sharing NoteEach external RefClk can feed up to 3 Quads (12 transceivers)MGTRefclk directly from an external pin via IBUFDSQuad (n+1)Quad (n)MGTRefClk comes from local pinsQuad (n-1)
16 PLL Selection: Typical Case Upstream and downstream are same rateXAUIPCIeAuroraMost other protocols…Power down TX PLL = Power Savings
17 PLL Selection: Fancy Case Upstream and downstream are different rates!HD-SDITransponder w/ FEC and w/o FEC ratesAdditional Flexibility
18 This output used by both TX and RX GTXRecallMGTRefClk is local, so we select MGTREFCLKRXFor Aurora, we use the same RefClk for TX and RX directionsTX PLL is powered down to save powerRemember…This output used by both TX and RXMGTRefClkfrom local pins
31 Reset Recommendation After Power-up and Configuration The entire GTX TX is reset automatically after configuration-providedTXPLLPOWERDOWN is Low. The supplies for the calibration resistor and calibrationresistor reference must be powered up before configuration to ensure correct calibration ofthe termination impedance of all transceivers.After Turning on a Reference Clock to the TX PLLThe reference clock source(s) and the power to the GTX transceiver(s) must be availablebefore configuring the FPGA. The reference clock must be stable before configurationespecially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators).If the reference clock(s) changes or GTX transceiver(s) are powered up after configuration,GTXTXRESET is asserted to allow the TX PLL(s) to lock.After Changing the Reference Clock to the TX PLLWhenever the reference clock input to the TX PLL is changed, the TX PLL must be resetafterwards to ensure that it locks to the new frequency. The GTXTXRESET port must beused for this purpose. Refer to “Reference Clock Selection,” page 55 for more details.After Assertion/Deassertion of TXPOWERDOWNAfter the TXPOWERDOWN signal is deasserted, GTXTXRESET must be asserted.TX Rate Change with the TX Buffer EnabledAfter TXRATEDONE is asserted, indicating the rate change has completed, the TX PLLoutput clock dividers must be reset followed by a TX PCS reset. To reset the clock dividers,GTXTEST is asserted for at least 16 TXUSRCLK2 cycles. To reset the TX PCS, TXRESETis asserted.To automatically reset the TX buffer after the rate change, the TX_EN_RATE_RESET_BUFattribute is set to “TRUE.”TX Rate Change with the TX Buffer Bypassedoutput clock dividers must be reset. Phase alignment must be performed again followedby reset of the TX PCS. See “TX Buffer Bypass,” page 104 for details on the rate changeprocedure.TX Parallel Clock Source ResetThe clocks driving TXUSRCLK and TXUSRCLK2 must be stable for correct operation.These clocks are often driven from an MMCM in the FPGA to meet phase and frequencyrequirements. If the MMCM loses lock and begins producing incorrect output, TXRESETmust be used to hold TX PCS in reset until the clock source is locked again.If the TX buffer is bypassed and phase alignment is in use, phase alignment must beperformed again after the clock source relocks.
32 TXBUFFER Remove phase difference between TXUSRCLK and XCLK Can be bypassed for low latency applicationAdvanced and some complex
33 Buffer Bypass StepsSet the following attributes with their values as follows:Set TXOUTCLK_CTRL to use either TXPLLREFCLK_DIV2 or TXPLLREFCLK_DIV1Set TX_XCLK_SEL to TXUSRSet TX_BUFFER_USE to FALSESet TX_PMADATA_OPT to TRUEAfter power-on, make sure TXPMASETPHASE and TXENPMAPHASEALIGN are driven Low.Make sure that the input port TXDLYALIGNDISABLE is driven High.Apply GTXTXRESET and wait for TXRESETDONE to go High.Wait for all clocks to stabilize, then assert TXDLYALIGNRESET for at least 16 TXUSRCLK2 clock cycles.Drive TXENPMAPHASEALIGN High.Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated.Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.Wait 32 TXUSRCLK2 clock cycles and then drive TXPMASETPHASE High.Wait the number of required TXUSRCLK2 clock cycles as specified in Table 3-20, and then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with TXUSRCLK.Drive TXDLYALIGNDISABLE Low.Optional: Keep TXDLYALIGNDISABLE High to disable the TX delay aligner.
35 Phase Re-alignment conditions GTXTXRESET is assertedTXPLLPOWERDOWN is deassertedThe clocking source changedThe line rate of the GTX TX transceiver changed
36 Phase Alignment after Line Rate changing 1. In non PCI Express mode, a TX rate change completion occurs when a TXRATEDONE pulse is detected.In PCI Express mode, a TX rate change completion occurs when a PHYSTATUS pulse is detected following a TXRATEDONE pulse.2. When a rate change completion is detected, assert TXDLYALIGNDISABLE.3. Assert GTXTEST for at least 16 TXUSRCLK2 cycles to reset the TX PLL output clock divider.Assert TXDLYALIGNRESET for at least 16 TXUSRCLK2 cycles to reset the TX delay aligner.5. Hold TXENPMAPHASEALIGN asserted.6. Wait for at least 32 TXUSRCLK2 cycles.7. Assert TXPMASETPHASE for the required TXUSRCLK2 cycles specified in Table 3-20.8. Deassert TXDLYALIGNDISABLE. (Optional: Hold TXDLYALIGNDISABLE asserted to disable the TX delay aligner.)9. Assert the TXRESET pulse and wait for TXRESETDONE to be asserted.10. For PCI Express mode, the “USER_PHYSTATUS” user signal must be generated and used as PIPE PHYSTATUS. Under normal operation, USER_PHYSTATUS follows the GTX PHYSTATUS signal. During rate change and subsequent TX phase alignment,USER_PHYSTATUS must gate the GTX PHYSTATUS and delay its assertion until after the TX phase alignment sequence is completed.
45 RXEQMIX Setting Determine the operating data rate. Determine the channel loss (board) in dB at data rate/2.This is the differential insertion loss from measured or extracted S-parameter data commonly referred to as Sdd21.Pick the appropriate RXEQMIX setting from the relative gain plot.Always make sure that the transmit amplitude is sufficient when picking modes with a higher gain because there is DC attenuation of the signal. Reference the absolute gain plot.Based on these results, the appropriate setting of RXEQMIX can be picked.
47 RX CDR Edge Sampler Data Sampler Scan Sampler Detect the Eye edge Real Data Sampling PointScan SamplerFor Margin
48 CDR Lock DetectionFinding known data in the incoming data stream (for example, commas or A1/A2 framing characters).Several consecutive known data patterns must be received without error to indicate a CDR lock.Using the LOS state machineIncoming data is 8B/10B encodedIf CDR is locked, the LOS state machine moves to the SYNC_ACQUIRED state and stays there.
52 Eye Margin Operating Steps Set proper RXREQMIXImproper RXREQMIX can lead to incorrect DFE operatingRun DFE with Auto-CalibrationTo get the max eye heightWith NO bit errorRun manual DFE with proper DFE settingCopy TAP monitors to TAP set portsAssert DFETAPOVRDSet RX_EYE_SCANMODE to 2’b01Via DRPModify RX_EYE_OFFSET to control scan sampling pointJudge by DFEEYEDACMONITOR[4:0]5’b11111 for 200mVMinimum input is 120mV (about 5’b10011)
54 RX Phase Alignment steps Set the following attributes with their values as follows:Set RXRECCLK_CTRL:2 byte or 4 byte – use RXRECCLKPMA_DIV21 byte – use RXRECCLKPMA_DIV1Set RX_BUFFER_USE to FALSE to bypass the RX elastic buffer.Set RX_XCLK_SEL to RXUSR.Make sure all the input ports RXENPMAPHASEALIGN and RXPMASETPHASE are driven LowMake sure that the input port RXDLYALIGNDISABLE is driven High.Reset the RX datapath using GTXRXRESET or the RXCDRRESET.If an MMCM is used to generate RXUSRCLK/RXUSRCLK2 clocks, wait for the MMCM to lock.Wait for the CDR to lock and provide a stable RXRECCLK.Assert RXDLYALIGNRESET for 20 RXUSRCLK2 clock cycles.Drive RXENPMAPHASEALIGN HighKeep RXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated. Driving RXENPMAPHASEALIGN Low causes phase align to be lostWait 32 RXRUSCLK2 clock cycles and then drive RXPMASETPHASE High for 32 RXUSRCLK2 cycles and then deassert it.Drive RXDLYALIGNDISABLE Low.
64 Quad used Priority FF484/FF784 Priority 1: MGT115This Quad should be used if any of the GTX transceivers in the device are used in the application. It contains the RCAL circuit that is required for the RX and TX internal termination resistors.Priority 2: MGT114/116Depending on availability in the package, these Quads have equal priority.
65 Quad used Priority FF1156/FF1759 Priority 1: MGT115This Quad should be used if any of the GTX transceivers in the device are used in the application. It contains the RCAL circuit that is required for the RX and TX internal termination resistors.Priority 2: MGT116/117/118If present in the Virtex-6 device, these Quads are connected in the package to the same power planes as MGT115, the north power plane group. Therefore they have equal priority. Because the north power planes need to be powered for MGT115, these Quads are also powered; therefore they can be used without additional power supply connections.Priority 3: MGT110/111/112/113/114These transceivers are connected to the south power planes. They should be used if all Quads on the north power planes have already been utilized. If any of these Quads are used, then all MGTAVCC_N and MGTAVTT_S pins need to be connected to the appropriate power supply voltage.