Contact Information Satnam Singh Email: firstname.lastname@example.org@microsoft.com Web: http://research.microsoft.com/~satnams http://research.microsoft.com/~satnams Lecture notes and other Bluespec information: http://cas.ee.ic.ac.uk/~ssingh http://cas.ee.ic.ac.uk/~ssingh
Objectives What is Bluespec? What is the design flow? What is it interesting or important? How is it different from VHDL/Verilog/SystemC/C-to-gate? What is it good for?
Overview Lectures 1 & 2: basics about Bluespec rules and their synthesis; examples. Lectures 3 & 4: Scheduling algorithm for rules; FSM design with Bluespec; Higher-order design with Bluespec
FPGAs as Co-Processors XD2000i FPGA in-socket accelerator for Intel FSB XD2000F FPGA in-socket accelerator for AMD socket F XD1000 FPGA co-processor module for socket 940
Microsoft High Level Synthesis Projects Kiwi: concurrent C# programs for control-oriented applications [Univ. Cambridge] shape analysis: synthesis of dynamic data structures (C) [MPI and CMU] Accelerator/FPGA: synthesis of data parallel programs in C++ [MSR Redmond]
ray of light Handel-C System-C CatapultC Occam Streams-C ROCC SPARK Bluespec Esterel Lola
Bluespec Spin-off from MIT Control language based on a collection of “atomic rules”. Expression language based on Haskell type system. Original syntax Haskell based. Current syntax inspired by System Verilog.
Using Bluespec bombastic.ee.ic.ac.uk goliath.ee.ic.ac.uk Binary: bsc License: at email@example.com (just in case) Website: bluespec.com Many thanks to Sam Bayliss for setup help.
Counter.bsv interface Counter_Interface; method int count(); endinterface: Counter_Interface (* synthesize *) module mkCounter (Counter_Interface); Reg#(int) c <- mkReg (0) ; rule increment (c < 10); c <= c + 1 ; $display("count = %d", c) ; endrule method int count () = c ; endmodule:mkCounter
always@(posedge CLK) begin if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN; if (b$EN) b <= `BSV_ASSIGNMENT_DELAY b$D_IN; end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin a = 32'hAAAAAAAA; b = 32'hAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on endmodule // rules1
(* synthesize *) module rules2 (Empty) ; Reg#(int) x <- mkReg (0) ; rule r1 ; x <= x + 1 ; endrule rule r2 ; x <= x + 2 ; endrule rule monitor ; $display ("x = %d", x) ; endrule endmodule
$ bsc -verilog Rules2.bsv Warning: "Rules2.bsv", line 2, column 8: (G0010) Rule "r2" was treated as more urgent than "r1". Conflicts: "r2" cannot fire before "r1": calls to x.write vs. x.read "r1" cannot fire before "r2": calls to x.write vs. x.read Warning: "Rules2.bsv", line 6, column 8: (G0021) According to the generated schedule, rule "r1" can never fire. Verilog file created: rules2.v