1. Configuring the External memory Controller of C6678 – C6670
CIV Application team July 2011

2. Agenda Short Overview of the external memory controller functionality
The MPAX registers
The MAR registers
Example 1 – Enable L2 cache for L2 shared memory
Example 2 – Disable L1 cache for L2 shared memory
Example 3 – Sharing very large DDR between multiple cores
Using software to configure external memory controller , using CSL API
Implementation of example 1 using CSL API

3. XMC – external memory Controller
The XMC responsible for:
Address extension/translation
Memory protection for addresses outside C66x
Shared memory access path
Cache and Pre-fetch support
User Control of XMC:
MPAX registers – Memory Protection and Extension Registers
MAR registers – Memory attributes registers
Each core has its own set of MPAX and MAR registers !

4. The MPAX Registers Translate between physical and logical address
16 registers (64 bits each) control (up to) 16 memory segment
Each register translates logical memory into physical memory for the segment
Segment definition in the MPAX registers:
Segment size – 5 bits – power of 2, smallest segment size 4K, up to 4GB
Logical base address – (up to 20 bits) the upper bits of the logical segment base address. The lower N bits are zero where N is determined by the segment size
For segment size 4K, N = 12 and the base address uses 20 bits
For segment size 8k, N=13 and the base address uses only 19 bits
For segment size 1G, N=20 and the base address uses only 2 bits

5. The MPAX Registers
Segment definition in the MPAX registers (continue):
Physical (replacement address) base address – (up to 24 bits) the upper bits of the physical (replacement) segment base address. The lower N bits are zero where N is determined by the segment size
For segment size 4K, N = 12 and the base address uses up to 24 bits
For segment size 8k, N=13 and the base address uses up to 23 bits
For segment size 1G, N=20 and the base address uses up to 6 bits
Permission – access type allowed in this address range
Three bits are dedicated for supervisor mode (write, read, execute)
Three bits are dedicated for user mode (write, read, execute)

6. The MPAX Registers Layout (from the user’s Guide)

7. The MPAX Registers
The following table summarizes the names and addresses of the MPAX registers:
MPAX description
Name
Address
Segment 0 lower 32 bits
XMPAXL0
0800_0000
Segment 0 upper 32 bits
XMPAXH0
0800_0004
Segment 1 lower 32 bits
XMPAXL1
0800_0008
Segment 1 upper 32 bits
XMPAXH1
0800_000c
Segment N lower 32 bits (N between 0 and 15)
XMPAXLN
0800_ N * 8
Segment N upper 32 bits(N between 0 and 15)
XMPAXHN
0800_ N * 8
Segment 15 lower 32 bits
XMPAXL15
0800_0078
Segment 15 upper 32 bits
XMPAXH15
0800_007c

8. The MAR Registers MAR = Memory Attributes Registers
256 registers (32 bits each) control 256 memory segment
Each segment size is 4MBytes, from logical address 0x to address 0xffffffff
The first 16 registers are read only. They control the core’s internal memories
Each register controls the cache-ability of the segment (bit 0) and the pre-fetch-ability (bit 3). All other bits are reserved and set to 0
All MAR bits are set to zero after reset

9. The MAR Registers Address Name Description Defines attributes for
The following table gives names, segments and addresses some of the MAR registers:
Address
Name
Description
Defines attributes for 0x
MAR0
MAR register 0
Local L2 (Ram) 0x
MAR1
MAR register 1
h-01ff ffffh
0x c
MAR15
MAR register 15
0f h-0fff ffffh 0x
MAR16
MAR register 16
h-10ff ffffh 0x
MAR17
MAR register 17
h-11ff ffffh 0x
MAR18
MAR register 18
h-12ff ffffh 0x
MAR128
MAR register 128
h-80ff ffffh 0x
MAR129
MAR register 129
h-81ff ffffh
0x fc
MAR255
MAR register 255
ff h-ffff ffffh

10. Example1 – Enable L2 Cache for MC Shared memory
Shared memory (MCMS RAM address 0c to 0c3f ffff) is L1 cacheable but not L2 cacheable.
Assume the user wants to make the first 1M of it L2 cacheable (and thus make it L3 memory)
And assume the user wants to protect this memory so that user and supervisor can read and write but not execute from this memory
The user must configure the MPAX and the MAR registers are follows:
To configure MPAX register
Use any MPAX register that is available, say register 3
Configure segment size to be 1M
Give a different logical address to the first 1Mbytes of shared L2
The logical address will present a memory that does not exist on the board
for example, if there is 512M bytes of external memory (from address 0xc to address 0xdfff ffff) chose the logical address to start at address 0xe

11. Example1 – Enable L2 Cache for MC Shared memory
To configure MPAX register (continue)
The protection bits are (two reserved bits, Supervisor read, write, execute, user read, write, execute)
Segment 3 registers are at addresses 0x (low register) and 0x c (high register)
Segment 3 has the following values:
Size = 1M = 10011b = 0x LSB of low register
7 bits reserved, written as zeros b
Logical base address 0x00E00 (12 bits, with the 20 zero bits from the size the logical base address is 0xE )
So the low register at address 0x is
Physical (replacement) base address 0x000c0 (16 bits, with the 20 bits from the size the physical base address is 0x0c000000)
So the high register at address 0x C is

12. Example1 – Enable L2 Cache for MC Shared memory
What about the MAR register?
The Mar register that correspondent to logical address 0xe is MAR 224 at address 0x This register controls 4M of memory, from 0xe to 0xe0ff ffff – even though only 1M of this memory is mapped into a “real” physical memory
Assume that the user wants to enable both, the cache and the pre-fetch, then the value of the MAR register is set to

13. Example2 – Disable L1 Cache for MC Shared memory
Shared memory (MCMS RAM address 0c to 0c3f ffff) is L1 cacheable. The coherency is not guaranteed between L1 cache and shared memory
If the user wants to use the shared memory to communicate between cores, it must manually manage the L1 coherency or disable the cache ability of the shared memory
In this example, we use the same MPAX registers as in example 1, however, we change the value of the correspondent MAR register (MAR 224 at address 0x ) from enable cache and pre-fetch to disable them.
Thus we set the MAR register to value 0x

14. Example3 – Sharing very large DDR for different cores
The DDR controller supports up to 8GB of external memory. But each core logical address is limited to 32 bits, where the external memory starts at address 0x , so the maximum external addressable external memory from each core is 2G.
If the user needs to use more external memory it can be done by giving each core a separate area in the external memory. So that for example, four cores can use 8G of memory
The following example shows how Each of the eight cores configures 1G off logical external memory to different part of the 8G physical external memory. This configuration can be for multi-channels application where the same code runs on all cores on different channels
To configure MPAX register for each core
Use any MPAX register that is available, say register 1
Configure segment size to be 1G
The logical address will start at 0x to 0xbfff ffff
The physical address depends on the core number
Assume full permission of the memory (r/w/e)

15. Example3 – Sharing very large DDR for different cores
Core 0 physical address will be from address 0x to address 0x0 3fff ffff
Core 1 physical address will be from address 0x to address 0x0 7fff ffff
Core 2 physical address will be from address 0x to address 0x0 bfff ffff
Core 3 physical address will be from address 0x0 C to address 0x0 ffff ffff
Core 4 physical address will be from address 0x to address 0x1 3fff ffff
Core 5 physical address will be from address 0x to address 0x1 7fff ffff
Core 6 physical address will be from address 0x to address 0x1 bfff ffff
Core 7 physical address will be from address 0x1 c to address 0x1 ffff ffff

16. Example3 – Sharing very large DDR for different cores
Segment 1 registers are at addresses 0x (low register) and 0x c (high register)
Segment 1 has the following values:
Size = 1G = 11101b = 0x1D - 5 LSB of low register
7 bits reserved, written as zeros b
Logical base address 0x (2 bits, with the 30 zero bits from the size the logical base address is 0x )
So the low register at address 0x for ALL the cores is
What about the higher register? It is a function of the core number
Core 0, Physical (replacement) base address 0x00000 (16 bits, with the 30 bits from the size the physical base address is 0x )
So the high register at address 0x C for core 0 is

17. Example3 – Sharing very large DDR for different cores
Core 1, Physical (replacement) base address 0x00001 (16 bits, with the 30 bits from the size the physical base address is 0x )
So the high register at address 0x C for core 1 is
Core 2, Physical (replacement) base address 0x00002 (16 bits, with the 30 bits from the size the physical base address is 0x )
So the high register at address 0x C for core 2 is
Core 7, Physical (replacement) base address 0x00007 (16 bits, with the 30 bits from the size the physical base address is 0x1 c )
So the high register at address 0x C for core 7 is

18. Using Software to configure XMC
Verify that the following path exists in your project (if not, add it)
PDK_INSTALL\packages
Where PDK_INSTALL is the path to the directory where the latest pdk was installed. A typical path looks like:
C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_11\packages
Include the CSL Auxiliary include file
#include <ti/csl/csl_cacheAux.h>

19. Using Software to configure XMC
Manipulate the Mar registers:
Defined in csl_cacheAux.h
CSL_IDEF_INLINE void CACHE_enableCaching ( Uint8  mar  ) 
CSL_IDEF_INLINE void CACHE_disableCaching ( Uint8  mar  ) 
CSL_IDEF_INLINE void CACHE_setMemRegionInfo (Uint8 mar, Uint8 pcx, Uint8 pfx)
Where Mar is 8 bits (0 to 255) number of the MAR register
Interesting enough, this is the base address shifted 24 places to the right
Pcx controls cache-ability, pfx controls pre-fetching
Example1 – Enable cache for DDR3 memory 0x to 0x80ff ffff
#define MAPPED_VIRTUAL_ADDRESS0 0x
CACHE_enableCaching ((MAPPED_VIRTUAL_ADDRESS0) >> 24);
Example2 – Disable cache for DDR3 memory 0x to 0x81ff ffff
#define MAPPED_VIRTUAL_ADDRESS1 0x
CACHE_disableCaching ((MAPPED_VIRTUAL_ADDRESS1) >> 24);
Example3 – Disable cache and enable prefetch for DDR3 memory 0x to 0x81ff ffff -
CACHE_setMemRegionInfo (((MAPPED_VIRTUAL_ADDRESS1) >> 24,0,1);
Note 1 – if CACHE_setMemRegionInfo is used, no need to use CACHE_disableCaching or CACHE_enableCaching
Note 2 – reset values (Mar 15 to 255) pre-fetch enable, cache disabled

20. Using Software to configure XMC
Manipulate the MPAX registers:
Defined in csl_xmcAux.h
CSL_IDEF_INLINE void
CSL_XMC_setXMPAXL ( Uint32  index, CSL_XMC_XMPAXHL *  mpaxh   )
Where index is one of the MPAX registers, 0 to 15 and CSL_XMC_XMPAXHL is a structure that is defined in the next slide:

21. /** This is the definition of CSL_XMC_XMPAXL */
typedef struct CSL_XMC_XMPAXL {
/** Replacement Address */
Uint32 rAddr;
/** When set, supervisor may read from segment */
Uint32 sr;
/** When set, supervisor may write to segment */
Uint32 sw;
/** When set, supervisor may execute from segment */
Uint32 sx;
/** When set, user may read from segment */
Uint32 ur;
/** When set, user may write to segment */
Uint32 uw;
/** When set, user may execute from segment */
Uint32 ux;
}CSL_XMC_XMPAXL;

22. Using Software to configure XMC
Manipulate the MPAX registers:
Defined in csl_xmcAux.h
CSL_IDEF_INLINE void
CSL_XMC_setXMPAXH ( Uint32  index, CSL_XMC_XMPAXH *  mpaxh   )
Where index is one of the MPAX registers, 0 to 15 and CSL_XMC_XMPAXH is a structure that is defined as follows:
typedef struct CSL_XMC_XMPAXH {
/** Base Address */
Uint32 bAddr;
/** Encoded Segment Size */
Uint8 segSize;
}CSL_XMC_XMPAXH;

23. Implementation of example 1 using CSL API
MPAX registers from the beginning of the presentation:
Use MPAX register 3
Segment size 1M (0x13 = 10011b)
Logical address 0xe (0x00e00)
Protection for supervisor and user, read, write, no execution ( )
Physical memory starts at 0x0c (0x000c0)

24. Implementation of example 1 using CSL API
Load CSl structures (there are API to load it with the appropriate values)
struct CSL_XMC_XMPAXL lowerStructure {
rAddr = 0x00e00
sr = 1;
sw= 1;
sx = 0 ;
ur = 1;
uw= 1;
ux = 0 ; };
struct CSL_XMC_XMPAXH higherStructure
bAddr = 0X000C0;
segSize= 0x13 ;

25. Implementation of example 1 using CSL API
Call CSl functions to set the MPAX registers
CSL_XMC_setXMPAXH (3, higherStructure) ;
CSL_XMC_setXMPAXL (3, owerStructure) ;