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A history of PC buses
I will in this presentation explain the major expansion buses used by the PC platform up until PCI Express.
From ISA to PCI Express
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2. ISA (Industry Standard Architecture) - 1981
Originated in the original IBM PC (8-bit / 4.77 MHz = 4 MB/s).
The ISA standard is based on PC/AT (16-bit / 8 MHz = 16 MB/s) – 1984
62 pins (8-bit PC ISA) or 98 pins (16-bit PC/AT ISA).
The ISA bus supported 1MB (PC/XT) / 16 MB (PC/AT) Memory and 64K I/O address spaces.
Lacked bandwidth for graphical user interfaces (MS Windows).
VL Bus (VESA Local Bus) gave some bandwidth respite on newer PC motherboards but was married to the 486/33 CPU bus.
VL Bus no longer worked when Pentium came out (60 MHz +) due to different CPU bus protocol.
Later, IBM created MCA as future-proof, CPU-independent alternative.
The initial expansion card bus used on the IBM PC in 1981 was a direct extension of the CPU bus.
In other words, the plug-in cards used the same data, address and control signal protocol as the 8088 CPU.
ISA is actually the name of the whole PC/AT architecture, not only the expansion bus interface.
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3. ISA (Industry Standard Architecture) – 1981 (cont.)
8-bit and 16-bit ISA slots
This is actually the original IBM 5170 PC/AT motherboard from 1984 which contains both 8-bit and 16-bit ISA slots.
Technically, the 8-bit slots are not ISA slots since ISA is a standard based on the PC/AT architecture which uses 16-bit slots.
Practically, both 8-bit and 16-bit slots are called “ISA” slots.
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4. ISA (Industry Standard Architecture) – 1981 (cont.)
16-bit ISA slot signals (PC/AT)
Note that the right ISA/AT bus slot additionally has 8 data, 7 address, 5 IRQ, 4 DRQ/DACK signals for added functionality over the original PC bus.
In total; 16 data and 24 address bits allows addressing 16 Mbytes of memory in a PC/AT computer (maximum for the CPU used by PC/AT).
The original PC/XT could only address 1 Mbytes of memory since only 20 address bits on 8088 CPU.
The 8088 is an internally 16-bit CPU with an external 8-bit data bus.
The 8088 can address 20 address bits by using 4 bit segment bit offset registers. See 8088 assembly book for details.
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5. MCA (Micro Channel Architecture) – 1987
Created by IBM to address deficiencies of the ISA bus (CPU-dependence and lack of performance).
Used by IBM PS/2 computers.
16/32 bits, 10 MHz, 20/40 MB/s
Software-based configuration (i.e. no IRQ, DMA jumpers).
Was not an open standard so never caught on with PC manufacturers.
Not backwards compatible with existing ISA expansion cards.
Was used by advanced server platforms due to high overall performance.
The ISA bus became too slow as the PC platform evolved.
By 1987, graphical user interfaces appear – a faster bus is needed for the graphics card.
Not compatible with large installed base of ISA cards – therefore not popular.
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6. MCA (Micro Channel Architecture) – 1987 (cont.)
32-bit MCA slots. Connector later reused by PCI.
Slide shows MCA motherboard slots.
Note that the connector is the same as later used by PCI.
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7. EISA (Extended Industry Standard Architecture) - 1988
Created by 3rd-party PC clone vendors.
32-bit / 8 MHz = 32 MB/s.
Software-based configuration (i.e. no IRQ, DMA jumpers).
EISA slots accepted ISA cards but EISA cards would not work in ISA slots.
Was never popular because ISA + VLB carried the PC platform until PCI came along.
Did see use in higher-performance server systems.
EISA was created by PC clone vendors as a solution to the problem of not enough graphics bandwidth on the ISA bus.
The bus protocol is backwards compatible with ISA but EISA cards would not work in existing ISA systems so never became popular.
Like MCA, EISA did see use in high-end server systems that did not have to be backwards compatible with ISA.
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8. EISA (Extended Industry Standard Architecture) – 1988 (cont.)
EISA slots – Accepts ISA cards too.
Note that EISA slots are 32-bit while ISA is 16-bit. The connector pitch is finer so not physically backwards compatible with ISA.
However, ISA cards fit in EISA slots via a two-layer connector (see next page).
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9. EISA (Extended Industry Standard Architecture) – 1988 (cont.)
EISA card – Does not fit in ISA slot.
EISA card do not fit in existing ISA-slot systems so never became popular.
Was mainly used in server systems where highest performance was more important than compatibility with older platforms.
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VLB (VESA Local Bus ) – 1992
32-bit, 33 MHz = 133 MB/s.
Created by Video Electronics Standards Association (VESA) for attaching high-performance graphics cards to ISA, and later PCI, motherboards.
Custom slot that extends the 16-bit ISA slot (see next slide).
Directly tied to the 486/33 memory bus – Doomed for other CPUs due to different CPU memory bus protocol.
The CPU memory bus only allowed one or two VLB card loads (due to loading and SI issues).
Difficult implementation, especially for 40/50 MHz 486 versions (instability common).
486DX2-66 and -100 used a 33 MHz front-side bus (x2/x3 internal clock) so compatible with VLB.
VLB is a third attempt to address the limited ISA bus bandwidth for graphics cards (after MCA and EISA).
This time, VLB was exclusively intended for graphics cards while ISA handled all other expansion cards.
VLB was a direct extension of the 486/33 bus which gave higher performance than ISA but again, just like ISA, dooms the VLB bus for future CPU bus architectures.
VLB could be used for higher frequency 486 CPUs (66.6 MHz, 99.9 MHz) by keeping the external bus frequency at 33 MHz and only double or triple the internal CPU frequency.
- This allowed the memory bus frequency and VLB to run at the same frequency
However, the Pentium used a different bus protocol so VLB died around 1993 when the Pentium came out.
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11. VLB (VESA Local Bus ) – 1992 (cont.)
32-bit VLB slot on ISA motherboard.
This is a 486 CPU motherboard. Note heat sink without cooler fan.
The ISA slots are 16-bits (has extension) + the VLB slots are the brown slots.
Note that the brown VLB connector is the same as later used by PCI. Also same as used by MCA but in different position so MCA cards would not fit.
Note that a VLB card uses both the ISA and VLB slots which makes the VLB cards very long and odd-looking (next page).
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12. VLB (VESA Local Bus ) – 1992 (cont.)
32-bit VLB Graphics Card
VLB connector left, PC/AT ISA connector middle, PC/XT ISA connector right. From 1995.
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13. PCI (Peripheral Component Interconnect) – 1992
Created by Intel (later PCI-SIG) to bring together best ideas from prior bus architectures.
32-bit, 33 MHz = 133 MB/s
Also supported 64-bit (while not commonly implemented) = 266 MB/s
Full plug-and-play (cards report Memory, IRQ, I/O requirements – device drivers and operating system make sure the cards get the resources they need and that no resource clashes occur).
Growing used PCI bandwidth eventually necessitated separate AGP graphics card bus.
PCI consolidated the VLB and ISA into a single, high-performance bus that lasted 10 years until PCI Express came out in 2003.
Not backwards compatible with anything but had support from many industry-leading companies via PCI-SIG so became instant success.
Supported up to 266 MB/s bandwidth and full plug-and-play.
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14. PCI (Peripheral Component Interconnect) – 1992 (cont.)
4x32-bit PCI slots + 4x16-bit ISA slots.
Slide shows 32-bit PCI and 16-bit ISA slots on same motherboard.
ISA bus must be connected to south bridge chip which clocks the ISA bus at 8 MHz while the Pentium is clocked at 60 MHz (also different bus protocol).
PCI bus is connected to host / PCI bridge chip to isolate between the CPU bus and PCI bus.
Note: Pentium CPU so likely from 1993 or so.
Note: Same connectors as MCA and VLB but now white.
Connector is positioned such that no other cards than PCI will fit.
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15. PCI (Peripheral Component Interconnect) – 1992 (cont.)
PCI bus now decoupled from CPU bus.
Processor waits while memory or I/O transaction is performed on the secondary PCI bus.
The Host CPU / PCI bridge generates bus transactions on the PCI (local) bus.
The Host CPU can continue executing instructions while the I/O is outstanding.
No longer need for VLB since graphics cards can be placed directly on high-bandwidth PCI bus.
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16. PCI (Peripheral Component Interconnect) – 1992 (cont.)
PCI Bus interface signals (32/64 bit data).
Memory or IO transactions are specified by Host CPU / PCI Bridge via combinations of the “Interface Control” signals.
Configuration space accesses are specified by Host CPU / PCI Bridge via dedicated IDSEL# signals (one per device).
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17. PCI (Peripheral Component Interconnect) – 1992 (cont.)
Configuration Space Registers & PnP
Plug and Play
1) Host CPU / PCI Bridge accesses a specific device’s configuration registers via dedicated physical IDSEL# signal.
2) The Host CPU / PCI Bridge is programmed by the operating system to map a range of system memory to a range of PCI memory address space.
This allows the host CPU to access a PCI device’s registers via memory writes/reads in the CPUs address space.
- The bridge responds to the CPUs memory accesses and performs secondary PCI bus transactions.
3) Vendor ID / Device ID uniquely define the device to the operating system which locates and loads the device driver (plug-and-play).
4) The operating system uses the BARs to allocate IO, Memory and interrupt resources for the device. Resources passed to PnP device driver.
5) The device driver accesses the memory-mapped or IO-mapped device registers as needed for normal operation.
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18. PCI-X (Peripheral Component Interconnect - Extended) - 1998
32/64-bit, 66/133/266/533 MHz (up to 4,266 MB/s).
PCI-SIG (IBM, Compaq, HP). Note: Intel wanted a better option.
Improved protocol over PCI (Split-Response Transactions, MSI signals interrupts via memory writes in host PCI bridge rather than dedicated INTx interrupt lines.).
Due to higher cost, normally only server PCs used 64-bit PCI-X.
Desktop systems migrated directly from PCI to PCI Express, bypassing PCI-X.
Wide buses resulted in difficult length matching of the bus signals (in worst case, violating Tsu/Th).
PCI-X reached practical frequency limit due to loading and skew of the wide buses
The wide buses tied up most I/O pins on the chipsets, limiting overall chip functionality.
PCI-X was created to increase the PCI bandwidth via higher bus frequency. Also new features such as Message Signaled Interrupts (MSI).
33 MHz was increased to 66/133/266/533 while the number of devices were decreased from 6 to 1 (in the case of 533 MHz).
Wide buses are hard to length-match which causes timing skew between signals. This limits the practical clock frequency of parallel buses.
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19. PCI-X (Peripheral Component Interconnect - Extended) – 1998 (cont.)
This slide shows how the PCI and PCI-X cards both can use 32-bit and 64-bit slots.
Both PCI and PCI-X can use 3.3V or 5V (or both in case of ‘universal’ cards).
3.3V signaling is faster so used on newer cards when maximum throughput is needed.
3.3V cards are keyed differently from 5V cards which ensures that wrong combination of card / slot is not possible.
Some cards are keyed for both 3.3V and 5V – these use multi-voltage drivers on the card.
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20. PCI-X (Peripheral Component Interconnect - Extended) – 1998 (cont.)
Fast and wide buses result in Tsu/Th timing skew between signals within the buses.
If the skew is too high, the interface will break!
All signals that are launched together must be latched together.
If a signal is delayed because it is longer then it will arrive later and Tsu will be smaller.
If a signal is shorter then it will arrive earlier and Th will be smaller.
If Tsu / Th are not met then meta-stability may result – the interface will break!
Meta-stability: the signal may register in wrong state or even change after a while.
Meta-stability may not clear up for many hundreds of nanoseconds – this causes trouble for following transactions too!
Due to these issues, newer interfaces use faster clocked serial links rather than wider parallel buses.
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PCI Express – 2004
Actually not a bus but a point-to-point link.
High-speed bi-directional serial link (2.5 / 5.0 / 8.0 Gbps per lane, 1 to 32 lanes).
Clock 8b/10b encoded within serial data stream.
Maintains software backwards compatibility of Configuration Space registers (Plug-and-Play).
Also software backwards compatible with regards to I/O and Memory-mapped device registers.
No length matching between lanes needed (separate lane-to-lane de-skew built into receiver).
After having used parallel buses over 21 years, PCI Express brought high-speed serial buses to the PC platform.
Parallel data is serialized via shift registers and sent in serial form at gigabit per second link frequencies.
8b/10b encoding was patented by IBM in 1984 and used in fibre channel and other serial link protocols.
8b/10b encoding allows data to be encoded in such a way that the clock signal can be embedded within the serial data sent.
This allows the receiver to synchronize its local receiver clock to the same clock the data was sent with, important at gigabit frequencies.
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PCI Express – 2004 (cont.)
PCI Express vs. PCI slots.
The PCIe connectors are very similar to, but not compatible with, the PCI connectors (different pitch and number of pins).
The PCI Express connectors use smaller pitch and are turned so not backwards compatible with any older connector type.
The yellow PCIe x16 slot is normally used for graphics card but can be used by any PCIe card.
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PCI Express – 2004 (cont.)
PCI Express bandwidth comparison.
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PCI Express – 2004 (cont.)
PCI Express 1.0a/1.1: 250 MB/s per lane (max 8 GB/s for 32 Lanes) – 2003/2005.
PCI Express 2.0: 500 MB/s per lane (max 16 GB/s for 32 Lanes)
PCI Express 3.0: 800 MB/s per lane (max 26 GB/s for 32 Lanes)
PCI Express 4.0: Again doubling transfer rate? Expected to be released 2014/2015.
Efficient and physically compact enables use for all platforms (mobile, desktop, server).
No longer need for separate AGP graphics bus slot (lots of available bandwidth).
This slide shows the performance per lane as well as maximum performance for a x32 lane link.
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25. International Test Instruments Corporation
A history of PC buses
This completes the overview of the legacy PC buses.
For a continued description of the PCI Express bus architecture, see the presentation “PCI Express 101”.
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