1. Memory Memory technologies
Static RAM (SRAM): Flip-Flops
Fast, expensive, used for caches
Dynamic RAM (DRAM): Charge stored in capacitor
Leackage requires periodic refreshing (< 2ms), slower
High density, cheap and used for main memory.
EPROM, EEPROM: Charge stored in an isolated gate
Storage of charge with high voltage
Erase: via ultraviolet light (EPROM), or electrically (EEPROM, Flash ROM)
Non-volatile memory
PROM: Burning of fuses
ROM: contents inserted during production
Flash:
Ein Flash-Speicher besteht aus einer bestimmten, von der Speichergröße abhängigen Anzahl einzelner Speicherelemente. Die Speicherung eines Bits innerhalb eines solchen Speicherelements erfolgt über ein Floating Gate, dem eigentlichen Speicherelement des Flash-FETs. Es liegt zwischen dem Steuer-Gate und der Source-Drain-Strecke und ist von dieser wie auch vom Steuer-Gate jeweils mittels einer Oxid-Schicht isoliert. Im ungeladenen Zustand des Floating Gate kann bei am Gate aufgesteuertem Transistor in der Source-Drain-Strecke (sog. Kanal) ein Strom fließen. Werden über das Steuer-Gate durch Anlegen einer hohen positiven (10..18V) Spannung Elektronen auf das Floating-Gate gebracht, so kann in der Source-Drain-Strecke auch bei aufgesteuertem Transistor kein Strom mehr fließen: das negative Potential der Elektronen auf dem Floating Gate wirkt der Spannung am Steuer-Gate entgegen und hält den Flash-Transistor geschlossen. Der ungeladene Zustand wird wieder erreicht, indem die Elektronen durch Anlegen einer hohen negativen Spannung über die Steuergate-Kanal-Strecke wieder aus dem Floating Gate ausgetrieben werden.

2. DRAM cell Architecture of a DRAM cell
Read destroys information, therefore it has to be written back.
Cycle time (time between two accesses) is larger than access time.

3. Architecture of a DRAM Chip

4. Memory Organization of PCs
SDRAM (Synchronous DRAM)
Synchron: All signals (RAS, Adresse …) are combined with a fixed clock cycle (PC100, PC133 …).
Access via North Bridge or an integrated memory controller
Frontside Bus
DIMM 1 or 2 rows
DIMM 1 or 2 rows
Prozessor
Chip Select
Chip Satz (North Bridge)
Address Data Control
Buffered und Registered DIMMs haben einen Puffer zwischen dem Bus und dem Speicher, um die Signale zu verbessern.
PC100 etc sind die Bezeichnungen für SDRAMS, DDR-SDRAMS verwenden DDR200 DDR266 … um die doppelte Datenrate anzuzeigen.
The main difference between SIMMs and DIMMs is that DIMMs have separate electrical contacts on each side of the module, while the contacts on SIMMs on both sides are redundant.
Data width is 64 Bit oder 8 Bytes
Chip Select determines the row
The row provides 8 Bytes

5. Memory Organization of PCs
Each row of a DIMM has 8 chips.
To provide 1 GB per row we use eight 1 Gbit SDRAM chips.
Each chip
8 data wires
internally organized in 4 banks with 256 Mbit. Each bank is organized in eight memory arrays.

6. Internal Organization of a GBit DRAM
1 GBit or 128 MByte chips
128 M = 227
27 adress lines
11 (2K) column
14 (16K) row
2 (4) memory field
8 Bit width
1 Bit width
16K rows, 2K columns

7. Access to DDR-SDRAM Read , Burst length=8
Burst Mode: transmission of 8 Bytes
DDR (Double Data Rate): Transmission with rising and falling edge of the clock signal
RAS-to-CAS-Delay (tRCD), CAS latency (tCL), RAS-to-Precharge-Latency (tRAS), Read-Cycle-time (tRC)
Precharge necessary because of differential lines
Bitleitung sind differentiell. Zuerst werden beide Leitungen auf den gleichen Pegel aufgeladen. Anschließend kommt es durch die Ladung in einer Leitung zu einer Spannungsdifferenz. Diese wird in den Schreib/Leseverstärkern registriert.

8. Access to DDR-SDRAM, Page Hit
Read, Burst length=8, Page Hit
Page: Data in the amplifiers of a row
All amplifiers of all blocks in the same bank
Hit: Data from the same row are accessed.

9. Access to DDR-SDRAM, Bank Overlap
Access to another bank can already start when the first burst is trasmitted.
In 2003, Intel released the i875P chipset, and along with it dual-channel DDR400. With a total bandwidth of 6400MB/sec, it marks the end of RDRAM as a technology with competitive performance.
Dual Channel Memory in heutigen Rechnern bedeutet zwei Bänke und übertragung von 128 Bit. Es gibt auch Speicherchips, die dual channel sind: eine Lese- und ein Write-Channel.
DDR2 SDRAM

10. Example Configuration
DDR400
200 MHz
400 MB/s
Frontside Bus (FSB800)
200 MHz
Quadpumped
4*64 Bit  6,4 GB/s
DIMM (DDR400 chips)
DIMM (PC3200)
3,2GB/s
Prozessor
i875P
DIMM
DIMM (PC3200)
DDR2 arbeiten intern mit geringerer Taktraten und ermöglichen so geringere Spannung und Leistungsaufnahme. Nach außen auch weiterhin Übertragung bei aufsteigender und fallender Taktflanke. Weiterhin bieten sie Potential für höhere Bandbreiten, da die interne Frequenz erhöht werden kann.
Bei DDR2-SDRAM taktet der I/O-Puffer mit der zweifachen Frequenz der Speicherchips. Bei dem älteren DDR-Standard erhielt man jeweils bei steigender als auch bei fallender Flanke des Taktsignals gültige Daten. Bei DDR2 erhält man nun zusätzlich dazu noch zwischen diesen Zuständen gültige Daten, was vier Datenworte pro Takt ergibt.
Zur Erhöhung der Taktraten und zur Senkung der elektrischen Leistungsaufnahme wurde die Signal- und Versorgungsspannung von DDR2-SDRAM auf 1,8 Volt verringert (bei DDR-SDRAM sind es 2,5 oder 2,6 Volt). Nebenbei führt die verringerte Spannung zu einer geringeren Wärmeentwicklung. Die elektrische Leistungsaufnahme sinkt auf für den Mobilbereich akkufreundlichere 247 mW (statt bisher 527 mW).
Zwei Kanäle mit je 3,2 GB/s

11. RAMBUS Rambus DRAM (RDRAM) is internally very similar to DDR SDRAM.
A point-to-point channel with higher clock rate and less pins in the memory controller is used.
Since Intel switched in 2003 to DDR RAM, RAMBUS was almost eliminated.
XDR-DRAM is used in the Sony PlayStation 3
XDR2-DRAM is used in high-end graphics cards and 3D TVs.
Rambus' XDR-DRAM, which is being incorporated into the Sony PlayStation 3 and supported with IBM’s "Cell" processor technology.
The Direct RDRAM, or RDRAM, features an architecture and a protocol that were designed to achieve high bandwidth. The Rambus channel architecture has a single-device upgrade granularity, offering engineers the ability to balance performance requirements against system capacity and component count. The narrow, high-performance channel also offers performance and capacity scalability through the use of multiple channels in parallel. In addition, the validation program created by Intel and Rambus promotes system stability by ensuring that devices and modules conform to published specifications. Although RDRAMs have a low pin count, a single device is capable of providing up to 1.6 GB/s bandwidth. Memory systems that use RIMMs (Rambus inline memory modules), also known as RDRAM modules, employ a narrow, uniform-impedance transmission line, the Rambus Channel, to connect the memory controller to a set of RIMMs. Low pin count and uniform interconnection topology allow easy routing and reduction of pin count on the memory controller. While a single channel is capable of supplying 1.6 GB/s of bandwidth, multiple channels can be used in parallel to increase this number. Systems that use, for example, the Intel 840 chipset have two parallel Rambus channels, and are able to handle up to 3.2 GB/s.
Providing high bandwidth from a single device also allows memory systems to be constructed from small numbers of RDRAMs. The Sony PlayStation 2 uses two RDRAM channels, each with a single RDRAM, to achieve a total of 3.2 GB/s memory bandwidth.
In order to ensure stability of RDRAM memory systems, design guidelines and a validation program have been put in place that surpass requirements set for previous memory technologies. Intel and Rambus have defined system specs to ensure robustness of RDRAMs and of the channel to the memory controller. In addition, they have created a rigorous validation programs for certification of RDRAMs and RIMM modules.
Due to the way RDRAM is designed, early implementations suffered from much higher memory latency when compared to contemporary SDR SDRAM and DDR SDRAM designs. While RDRAM's very high bandwidth allowed this effect to be masked to a certain degree, randomly accessed memory cells would suffer large performance drops with RDRAM, making SDR SDRAM or DDR SDRAM a better choice. Latency became worse as additional RIMM's were added to the system, further hurting performance.
Later designs mitigated the latency issue to the point where it was mostly competitive with DDR SDRAM, but by then RDRAM's parent company Rambus had largely alienated hardware manufacturers due to its litigious nature. Consumer sentiment turned against Rambus in the same manner and also because of RDRAM's higher price compared to other memory types. As of 2004, Intel has essentially abandoned RDRAM entirely, with all new products using DDR SDRAM or DDR-2 SDRAM.
12,8 GBytes/s bandwidth

12. Static Memory One bit is implemented by 6 MOSFET transistors
No refresh
Very fast access times.
Expensive compared to DRAM
Used for caches
10 – 30 nsec Zugriffszeit

13. FLASH Memories Write Read High negative voltage removes the charge
A high voltage (10-13V) between gate and source lets electrons tunnel into the floating gate.
Read
The charge of the floating gate partially cancels the electric field from the control gate.
Thus, a higher voltage is required to make the channel conduct.
With a certain threshold voltage, the state of the transistor can be sensed.
High negative voltage removes the charge
Reset is done for 16 KB blocks.
Isolation is damaged by reset.

14. NOR vs NAND
NAND
more compact since less wires, although more transistors
read: offset power for other FETs
NOR
NAND read: all word lines are set to a voltage so that the charge does not matter. Only for the requested word, the voltage is lowered, so that the charge matters. Thus, if it is charged, the bit line gets low.
NOR read: each cell can be read individually.

15. Single and Multi Level Cells (SLC / MLC)
SLCs store one bit
MLCs store up to four bits
Instead of only checking the presence of the current, the strenght is sensed. Thus, more presice measurement is required.
The states are determined by the amount of charge in the floating gate. Thus, precise control of the charge deposit is required.
Higher density, lower cost
Larger bit error ratio
Lower write speeds, lower number of program-erase cycles and higher power consumption

16. NAND Flash Performance
Organized in pages (512 or 2048 bytes)
Writes are performed to entire pages. µs
Reset done in larger blocks
1-2 ms
Reads are fast
25 µs for 4KB

17. NAND Flash Durability 10.000 – 1.000.000 writes for each cell Solution
Wear leveling: distribution of writes to same address over multiple cells.
Spare cells

18. FLASH Usage Solid State Disc (SSD) Hybrid Disc Turbo Speicher
Up to 512 GB (300 €), 1TB (800 €)
Up to 520 MB/s Lesen und 400 MB/s Schreiben
Lower energy consumtion in idle and active mode as normal discs
Comparison with HDD see resources in Mindmap
Hybrid Disc
Nonvolatile buffer for write accesses
Or used as permanent cache controlled by the OS
Turbo Speicher
PCIe-MiniCard from Intel to speedup boot process.