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ECEA Stick Diagrams VLSI design aims to translate circuit concepts onto silicon stick diagrams are a means of capturing topography and layer information - simple diagrams Stick diagrams convey layer information through color codes (or monochrome encoding)
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Encoding for nMOS process
Stick Encoding Layer Mask Layout Encoding Thinox Polysilicon Metal1 Contact cut NOT applicable Overglass Implant Buried contact ECEA
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Not Shown in Stick Diagram
Encoding for pMOS process Stick Encoding Layer Mask Layout Encoding P-Diffusion Not Shown in Stick Diagram P+ Mask Metl2 VIA Demarcation Line P-Well Vdd or GND CONTACT ECEA
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For reference : an nMOS Inverter coloured stick diagram
* Note the depletion mode device Vout Vdd = 5V Vin ECEA
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Only metal and polysilicon can cross the dimarcation line.
CMOS Inverter coloured stick diagram ECEA
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Stick diagram -> CMOS transistor circuit
Vdd = 5V Vout Vdd = 5V Vin pMOS Vin Vout nMOS ECEA
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Lambda (λ)-based design rules
All paths in all layers will be dimensioned in λ units and subsequently λ can be allocated an appropriate value compatible with the feature size of the fabrication process. ECEA
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Transistor design rules
Thinox Metal 1 n-diffusion p-diffusion 3 λ 2 λ 3 λ 3 λ Minimum distance rules between device layers, e.g., polysilicon metal metal metal diffusion diffusion and minimum layer overlaps are used during layout 2 λ 3 λ Metal 2 2 λ 4 λ 2 λ 4λ 2 λ Polysilicon 4 λ ECEA
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nMOS transistor mask representation
gate drain source polysilicon metal Contact holes diffusion (active region) ECEA
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Contact Cuts Three possible approaches – Poly to Metal
Metal to Diffusion Buried contact (poly to diff) or butting contact (poly to diff using metal) ECEA
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Layout Design rules & Lambda ()
2 Minimize spared diffusion Use minimum poly width (2) Width of contacts = 2 Multiply contacts ECEA
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Layout Design rules & Lambda ()
3 6 6 2 2 All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3 ECEA
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Layout Design rules & Lambda ()
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CMOS Layout N Well P diff Contacts Metal Poly N diff P Substrate ECEA
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Layout Design rules & Lambda ()
Width of pMOS should be twice the width of nMOS L min Wpmos=2 Wnmos Same N and P alters symmetry ECEA
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Lambda Based Design Rules
Design rules based on single parameter, λ Simple for the designer Wide acceptance Provide feature size independent way of setting out mask Minimum feature size is defined as 2 λ Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be contacted ECEA
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CMOS Inverter Mask Layout
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CMOS Layout Design CMOS IC are designing using stick diagrams.
Different color codes for each layer. Lamda/micron grid. ECEA
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CMOS AN2 (2 i/p AND gate) Mask Layout
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nMOS Inverter coloured stick diagram
* Note the depletion mode device Vout Vdd = 5V Vin ECEA
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Two-way selector with enable
X off on on on off A E off on Y A’ E=0 A=0|1 ECEA
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Static CMOS NAND gate ECEA
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Static CMOS NOR gate ECEA
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Static CMOS Design Example Layout
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Layout 2 (Different layout style to previous but same function being implemented)
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Complex logic gates layout
Ex—F=AB+E+CD Eulerpaths Circuit to graph (convert) Vertices are source/Drain connections Edges are transistors Find p and n Eulerpaths ECEA
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VirtuosoFab Touch the deep submicron technology 3D fabrication process simulator with cross sectional viewer. Step-by-step 3-D visualization of fabrication for any portion of layout. ECEA
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2D Cross Section NMOS Transistor Metal Layer Contacts Poly N Diffusion
ECEA
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