1. Chapter 20 TSMC 5NM Yield analysis Dr. Wei-E Wang 1

2. Yield Limiters Process-limited yield Contaminants (used to be bad, now is somewhat resolved) Inadequate process margin ( key limiters) Cobalt (Intel’s Achilles heel ) Multi-patterning (Intel/Samsung’s Achilles heel ) Poor mask/PDK design (see below) Design-limited yield PDK/Mask design (everyone) 2 https://m.eet.com/media/1184149/inside_eedesign7.pdf https://scholarwor ks.umass.edu/cgi/ viewcontent.cgi?r eferer=https://ww w.google.com/&h ttpsredir=1&articl e=1863&context= theses

3. Yield Limiters Contaminants (used to be bad, now is somewhat resolved) Textbook formulae no longer applicable 3 https://scholarwor ks.umass.edu/cgi/ viewcontent.cgi?r eferer=https://ww w.google.com/&h ttpsredir=1&articl e=1863&context= theses https://www.mksinst.com/n/wafer-surface-cleaning TSMC 5NM

4. Yield Limiters Cobalt (Intel’s Achilles heel ) Cobalt fill in high aspect ratio difficult Void formation can be a big issue Intel invented this process but failed to deliver yield performance Intel lost 10NM markets (CEO was kicked out) TSMC, as the copycat, did a better job No issues, TSMC became world No.1 4 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Cobalt fill/reflow

5. Yield Limiters Multi-patterning (Intel/Samsung’s Achilles heel ) Multiple patterning (SAQP) Multiple passes killed the yield TSMC applied EUV successfully (the other two could not make it work) to reduce the number of masks (passes) significantly Their maskless reticle is the key enabler 5 SAQP 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

6. TSMC 5NM Yield outstanding World class DD (defect density) = 0.5/cm 2 TSMC DD ~ 0.1/cm 2 NVidia 10: ~80% Yield Zen2 Chiplet: ~94% Yield 6 https://www.anandtech.com/show/16028/better-yield-on-5nm- than-7nm-tsmc-update-on-defect-rates-for-n5 Anything below 0.5/cm 2 is usually a good metric, and we’ve seen TSMC pull some interesting numbers, such as 0.09 / cm 2 on its N7 process node only three quarters after high volume manufacturing0.09 0.1/cm 2 https://www.anandtech.com/show/15219/early-tsmc- 5nm-test-chip-yields-80-hvm-coming-in-h1-2020 Yield =80%

7. Yield formulae from Textbook ITRS 建議使用以上 Negative-Binomial (NB) distribution 產生的良率公式 7 TSMC 5NM

8. Yield model: negative binomial Y = f (A c ， D) D = defect density Ac = critical area (in which a defect occurring has a high probability of resulting in a fault) ， ” Murphy suggests Y : Okabe suggests f(D) : 8 Fundamentals of Semiconductor Manufacturing and Process Control ， Spanos and May

9. My Yield Model for TSMC 5NM Yield Known: TSMC yield = 80% ， die size = 10mmx10mm (Apple A13) Question: What will the yield curve look like if the die area changes? Solution: Let’s use Poisson distribution to estimate defect density D 0 0.8=exp(-1cm*1cm*D 0 ) D 0 = - ln(0.8) = 0.223/cm 2 9 A (die size in cm 2 ) yield curve

10. In general: Yield reduces with increasing die size Dies size vs yield FPGA (Xilinx, VU19P) die size super large = 9cm 2 Very low yield and this very expensive New Chiplet ideas Very small dis size  yield much better 10 TSMC 5NM

11. Yield Limiters for the Next Generation Variations will be the Scaling and Yield Limiter RDF: Random dopant fluctuation LER: line edge roughness variation Avt from Vt sigma: multi-Vt variation GAA will still be inadequate 11