1.  Field Effect Transistor (FET)  Junction Field Effect Transistor (JFET)  Construction of JFET  Theory of Operation  I-V Characteristic Curve  Pinch off Voltage (V P )  Saturation Level  Break Down Region  Ohmic Region  Cut off Voltage  Advantages  Disadvantages  Application of JFET OUTLINE

2. INTRODUCTION The ordinary or bipolar transistor has two main disadvantage. It has a low input impedance It has considerable noise level To overcome this problem Field effect transistor (FET) is introduced because of its: High input impedance Low noise level than ordinary transistor And Junction Field Effect Transistor (JFET) is a type of FET.

3. FET  FET is a voltage controled device.  It consists of three terminal. Gate Source Drain  It is classified as four types. JFET MOSFET Field Effect Transistor (FET)

4.  Junction Field Effect Transistoris a three terminal semiconductor device in which current conducted by one type of carrier i.e. by electron or hole. Junction Field Effect Transistor (JFET)

5.  Source: The terminal through which the majority carriers enter into the channel, is called the source terminal S.  Drain: The terminal, through which the majority carriers leave from the channel, is called the drain terminal D.  Gate: There are two internally connected heavily doped impurity regions to create two P-N junctions. These impurity regions are called the gate terminal G.  Channel: The region between the source and drain, sandwiched between the two gates is called the channel. Construction of JFET

6.  JFET has two types : n- Channel JFET p- Channel JFET Types of JFET

7. Symbol of JFET

8.  JFET is a voltage controlled device i.e. input voltage (V GS ) control the output current (I D ).  In JFETs, the width of a junction is used to control the effective cross- sectional area of the channel through which current conducts.  It is always operated with Gate-Source p-n junction in reverse bias.  Because of reverse bias it has high input impedance.  In JFET the gate current is zero i.e. I G =0. Features of JFET

9. (i)When gate-source voltage (V GS ) is applied and drain-source voltage is zero i.e. V DS = 0V  When V GS = 0v, two depletion layers & channel are formed normally.  When V GS increase negatively i.e. 0 V > V GS > V GS(off), depletion layers are also increased and channel will be decrease.  When V GS =V GS(off), depletion layer will touch each other and channel will totally removed. So no current can flow through the channel. Theory of Operation Depletion layer

10. (ii)When drain-source voltage ( V DS ) is applied at constant gate-source voltage ( V GS ) :  Now reverse bias at the drain end is larger than source end and so the depletion layer is wider at the drain end than source end.  When V DS increases i.e. 0v < V DS < V P, depletion layer at drain end is gradually increased and drain current also increased.  When V DS = V P the channel is effectively closed at drain end and it does not allow further increase of drain current. So the drain current will become constant. Theory of Operation

11. It is the curve between drain current (I D )and drain-source voltage (V DS )for different gate-source voltage (V GS ). It can be characterized as:  For V GS =0v the drain current is maximum. It’s denoted as I DSS and called shorted gate drain current.  Then if V GS increases Drain current I D decreases (I D < I DSS ) even though V DS is increased.  When V GS reaches a certain value, the drain current will be decreased to zero.  For different V GS, the I D will become constant after pinch off voltage (V P ) though V DS is increased. I-V Characteristic Curve

12. Fig: Transfer Characteristic Curve Transfer Characteristic Curve  This curve shows the value of I D for a given value of V GS.

13.  It is the minimum drain source voltage at which the drain current essentially become constant. Pinch off Voltage (V P ) Pinch off Voltage

14.  After pinch off voltage the drain current become constant, this constant level is known as saturation level. Saturation Level

15.  The region behind the pinch off voltage where the drain current increase rapidly is known as Ohmic Region. Ohmic Region

16. Break Down Region  It is the region, when the drain-source voltage (V DS ) is high enough to cause the JFET’s resistive channel to breakdown and pass uncontrolled maximum current.

17.  The gate-source voltage, when the drain current become zero is called cut- off voltage. Which is usually denoted as V GS (off). Cut off Voltage Here I D become Zero

18. JFET Drain Current I D In SATURATION REGION of FET drain current (I D ) will be given as: Therefore JFET is Square Law Device In JFET as I D decreases as a parabolic variation Transfer characteristics are plotted only for SATURATION REGION I D is majority carrier current and it decreases with temperature As temperature increases, majority carrier concentration will remain almost independent of temperature but mobility of charge carrier decreases with temperature. Hence I D decrease with temperature 18

19. PINCH OFF VOLTAGE (V P ) Pinch off Voltage is minimum V DS (Drain to Source voltage) where I D enter into saturation region Therefore V P is function of V GS In JFET maximum V P is V P(0) In JFET when V GS applied V P is reduced 19

20. Working During PINCH OFF As V DS increases above V P two depletion layer will come extremely closer but they will not touch each other. This is due to large ELECTRIC FIELD INTENSITY created at upper end of channel and pointing towards source. Field is expanding over length L’ of depletion layer and it is preventing 2 depletion layer from touching each other. Therefore in SATURAION REGION of JFET 2 depletion layer will not be touching each other. During pinch off, channel width becomes very narrow but velocity of electron increases and these electron moving with high velocity with narrow channel width and reaching DRAIN. 20

21. Working During PINCH OFF Now DRAIN is receiving maximum number of electrons from channel and therefore in SATURATION region I D will remain almost constant. 21

22. Parameters of JFET Trans-Conductance (g mo ) Dynamic Output Resistance (r d ) Amplification Factor (μ) 22

23. Trans-Conductance (g m ) Transconductance is the ratio of change in drain current (δI D ) to change in the gate to source voltage (δV GS ) at a constant drain to source voltage (V DS = Constant). 23

24. This is the ratio of change of drain to source voltage (δV DS ) to the change of drain current (δI D ) at a constant gate to source voltage (V GS = Constant). The ratio is denoted as r d. 24 Dynamic Output Resistance

25. Amplification Factor The amplification factor is defined as the ratio of change of drain voltage (δV DS ) to change of gate voltage (δV GS ) at a constant drain current (I D = Constant). There is a relation between transconductance (g m ) and dynamic output resistance (r d ) and that can be established in the following way. 25

26.  It is simpler to fabricate, smaller in size.  It has longer life and higher efficiency.  It has high input impedance.  It has negative temperature coefficient of resistance.  It has high power gain. Advantages

27.  Greater susceptibility to damage in its handling.  JFET has low voltage gain. Disadvantages

28.  Voltage controlled resistor  Analog switch or gate  Act as an amplifier  Low-noise amplifier  Constant current source Application of JFET