1. INTRODUCTION TO VERILOG HDL
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2. “Gateway Design Automation” company Simulation environment
VERILOG HDL
Beginning: 1983
“Gateway Design Automation” company
Simulation environment
Comprising various levels of abstraction
Switch (transistors), gate, register-transfer, and higher levels
Three factors to success of Verilog
Programming Language Interface (PLI)
Extend and customize simulation environment
Close attention to the needs of ASIC foundries
“Gateway Design Automation” partnership with Motorola, National, and UTMC in
Verilog-based synthesis technology
“Gateway Design Automation” licensed Verilog to Synopsys
Synopsys introduced synthesis from Verilog in 1987
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3. What is Verilog?
Verilog is a HDL- hardware description language to design the digital system.
VHDL is other hardware description language.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages
Verilog was introduced in 1985 by Gateway Design System Corporation
VHDL
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
Developed under contract from DARPA
IEEE standard
Public domain
Other EDA vendors adapted VHDL
“Gateway” put Verilog in public domain
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4. Market divided between Verilog & VHDL VHDL mostly in Europe
Today
Market divided between Verilog & VHDL
VHDL mostly in Europe
Verilog dominant in US
VHDL
More general language
Not all constructs are synthesizable
Verilog:
Not as general as VHDL
Most constructs are synthesizable
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5. HDL Emergence
The need to a standardized language for hardware description
Verilog® and VHDL
Simulators emerged
Usage: functional verification
Path to implementation: manual translation into gates
Logic synthesis technology
Late 1980s
Dramatic change in digital design
Design at Register-Transfer Level (RTL) using an HDL
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6. Typical design flow Design specification Behavioral description
RTL description
Functional verification and testing
Logic synthesis
Gate-level netlist
Logical verification and testing
Floor planning, automatic place & route
Physical layout
Layout verification
Implementation
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7. Importance of HDL Retargeting to a new fabrication technology
Functional verification earlier in the design cycle
Textual concise representation of the design
Similar to computer programs
Easier to understand
Trends
Design at behavioral level
Formal verification techniques
Very high speed and time critical circuits
e.g. microprocessors
Mixed gate-level and RTL designs
Hardware-Software Co-design
System-level languages: SystemC, SpecC, …
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8. Verilog IEEE 1364-2001 is the latest Verilog HDL standard
Verilog is case sensitive (Keywords are in lowercase)
The Verilog is both a behavioral and a structure language
Popularity of Verilog HDL
Verilog HDL
General-purpose
Easy to learn, easy to use
Similar in syntax to C
Allows different levels of abstraction and mixing them
Supported by most popular logic synthesis tools
Post-logic-synthesis simulation libraries by all fabrication vendors
PLI to customize Verilog simulators to designers’ needs
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9. Difference between VERILOG and VHDL
Verilog is similar to C- language.
VHDL is similar to Ada- (ada is a structured, statically typed, imperative, wide-spectrum, and object-oriented high-level computer programming language, extended from Pascal )
Many feel that Verilog is easier to learn and use than VHDL.
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10. Design Methodologies
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11. 4 Bit Ripple Counter
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12. T-flipflop and the Hierarchy
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13. Elements of Verilog-logic values
0: zero, logic low, false, ground
1: one, logic high, power
X: unknown
Z: high impedance, unconnected, tri-state
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14. Elements of verilog- data type
Nets
Nets are physical connections between devices
Many types of nets, but all we care about is wire.
Declaring a net
wire [<range>] <net_name> ;
Range is specified as [MSb:LSb]. Default is one bit wide
Registers
Implicit storage-holds its value until a new value is assigned to it.
Register type is denoted by reg.
Declaring a register
reg [<range>] <reg_name>;
Parameters are not variables, they are constants.
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15. Verilog Primitives and or not buf xor nand nor xnor bufif1, bufif0
Basic logic gates only
and or
not
buf
xor
nand
nor
xnor
bufif1, bufif0
notif1, notif0
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16. <size>’<radix> <value>
Numbers in Verilog
<size>’<radix> <value>
8’h ax = 1010xxxx
12’o 3zx7 = 011zzzxxx111
Binary  b or B
Octal  o or O
Decimal  d or D
Hexadecimal  h or H
No of
bits
Consecutive chars
0-f, x, z
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17. Logical Operators &&  logical AND ||  logical OR !  logical NOT
Operands evaluated to ONE bit value: 0, 1 or x
Result is ONE bit value: 0, 1 or x
A = 1; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x
but C&&B=0
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18. Bitwise Operators (i) &  bitwise AND |  bitwise OR ~  bitwise NOT
^  bitwise XOR
~^ or ^~  bitwise XNOR
Operation on bit by bit basis
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19. Bitwise Operators (ii)
a = 4’b1010;
b = 2’b11;
c = a & b;
c = ~a;
a = 4’b1010;
b = 4’b1100;
c = a ^ b;
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20. shift, Conditional Operator
>>  shift right
<<  shift left
a = 4’b1010;
d = a >> 2;// d = 0010,c = a << 1;// c = 0100
cond_expr ? true_expr : false_expr A 1 Y
Y = (sel)? A : B; B
sel
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21. Keywords Note : All keywords are defined in lower case Examples :
module, endmodule
input, output, inout
reg, integer, real, time
not, and, nand, or, nor, xor
parameter
begin, end
fork, join
specify, endspecify
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22. Keywords module – fundamental building block for Verilog designs
Used to construct design hierarchy
Cannot be nested
endmodule – ends a module – not a statement
=> no “;”
Module Declaration
module module_name (module_port, module_port, …);
Example: module full_adder (A, B, c_in,
c_out, S);
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23. Verilog keywords Input Declaration Scalar
input list of input identifiers;
Example: input A, B, c_in;
Vector
input[range] list of input identifiers;
Example: input[15:0] A, B, data;
Output Declaration
Scalar Example: output c_out, OV, MINUS;
Vector Example: output[7:0] ACC, REG_IN, data_out;
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24. Types verilog coding Behavioral
Procedural code, similar to C programming
Little structural detail (except module interconnect)
Dataflow
Specifies transfer of data between registers
Some structural information is available (RTL)
Sometimes similar to behavior
Structural (gate,switch)
Interconnection of simple components
Purely structural
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25. Hierarchical Design Top Level Module Sub-Module 1 2 Basic Module 3
E.g.
Full Adder
Half Adder
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26. f Module in1 in2 inN out1 out2 outM my_module
module my_module(out1, .., inN);
output out1, .., outM;
input in1, .., inN;
.. // declarations
.. // description of f (maybe
.. // sequential)
endmodule f
in1
in2
inN
out1
out2
outM
my_module
Everything you write in Verilog must be inside a module
exception: compiler directives
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27. Modules Verilog supported levels of abstraction
Behavioral (algorithmic) level
Describe the algorithm used
Very similar to C programming
Dataflow level
Describe how data flows between registers and is processed
Gate level
Interconnect logic gates
Switch level
Interconnect transistors (MOS transistors)
Register-Transfer Level (RTL)
Generally known as a combination of behavioral+dataflow that is synthesizable by EDA tools
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28. Stimulation-Testbench styles
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29. Instances module ripple_carry_counter(q, clk, reset); output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);
endmodule
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30. Instances
module TFF(q, clk, reset); output q; input clk, reset; wire d; DFF dff0(q, d, clk, reset); not n1(d, q); // not is a Verilog provided primitive. endmodule
module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule
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31. Instances Illegal instantiation example:
Nested module definition not allowed
Note the difference between module definition and module instantiation
// Define the top level module called ripple carry counter. It is illegal to define the module T_FF inside this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
<module T_FF internals>
endmodule // END OF ILLEGAL MODULE NESTING
endmodule
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32. Example
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33. Example(Contd) module stimulus; reg clk; reg reset; wire[3:0] q;
// instantiate the design block
ripple_carry_counter r1(q, clk, reset);
// Control the clk signal that drives the design block.
initial clk = 1'b0;
always #5 clk = ~clk;
// Control the reset signal that drives the design block
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $stop;
end
initial // Monitor the outputs
$monitor($time, " Output q = %d", q);
endmodule
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34. Verilog coding for all gate
module gates(a, b, y1, y2, y3, y4, y5, y6, y7);
input [3:0] a, b;
output [3:0] y1, y2, y3, y4, y5, y6, y7;
/* Seven different logic gates acting on four bit busses */
assign y1= ~a; // NOT gate
assign y2= a & b; // AND gate
assign y3= a | b; //  OR gate
assign y4= ~(a & b); // NAND gate
assign y5= ~(a | b); // NOR gate
assign y6= a ^ b; // XOR gate
assign y7= ~(a ^ b); // XNOR gate
endmodule
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35. Example: Half Adder Half Adder A B S C module half_adder(S, C, A, B);
output S, C;
input A, B;
wire S, C, A, B;
assign S = A ^ B;
assign C = A & B;
endmodule
Half
Adder A B S C
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36. Example: Full Adder Half Adder ha2 A B S C Adder 1 ha1 in1 in2 cin
cout
sum I1 I2 I3
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;
wire sum, cout, in1, in2, cin;
wire I1, I2, I3;
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);
assign cout = I2 || I3;
endmodule
Module
name
Instance
name
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37. 4-bit adder Example module add4 (s,c3,ci,a,b)
input [3:0] a,b ; // port declarations
input ci ;
output [3:0] s : // vector
output c3 ;
wire [2:0] co ;
add a0 (co[0], s[0], a[0], b[0], ci) ;
add a1 (co[1], s[1], a[1], b[1], co[0]) ;
add a2 (co[2], s[2], a[2], b[2], co[1]) ;
add a3 (c3, s[3], a[3], b[3], co[2]) ;
endmodule
Simpler than VHDL
Only Syntactical Difference a0 a1 a2 a3 c3 ci
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38. Assignments
Continuous assignments assign values to nets (vector and scalar)
They are triggered whenever simulation causes the value of the right-hand side to change
Keyword “assign”
e.g. assign out = in1 & in2;
Procedural assignments drive values onto registers (vector and scalar)
They Occur within procedures such as always and initial
They are triggered when the flow of execution reaches them (like in C)
Blocking and Non-Blocking procedural assignments
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39. Assignments (cont.) Procedural Assignments
Blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement
Nonblocking assignment statement (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit
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40. Delay based Timing Control
Delay Control (#)
Expression specifies the time duration between initially encountering the statement and when the statement actually executes.
Delay in Procedural Assignments
Inter-Statement Delay
Intra-Statement Delay
For example:
#10 A = A + 1;
A = #10 A + 1;
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41. Example: Half Adder, 2nd ImplementationB S C
module half_adder(S, C, A, B);
output S, C;
input A, B;
wire S, C, A, B;
xor #2 (S, A, B);
and #1 (C, A, B);
endmodule
Assuming:
XOR: 2 t.u. delay
AND: 1 t.u. delay
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42. Combinational Circuit Design
Outputs are functions of inputs
Examples
MUX
decoder
priority encoder
adder
comb.
circuits
inputs
Outputs
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43. Procedural Statements: if
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;
wire [1:0] sel;
or sel)
if (sel == 0)
out = in[0];
else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule
if (expr1)
true_stmt1;
else if (expr2)
true_stmt2; ..
else
def_stmt;
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44. Procedural Statements: case
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;
wire [1:0] sel;
or sel)
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
case (expr)
item_1, .., item_n: stmt1;
item_n+1, .., item_m: stmt2; ..
default: def_stmt;
endcase
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45. Decoder 3-to 8 decoder with an enable control
module decoder(o,enb_,sel) ;
output [7:0] o ;
input enb_ ;
input [2:0] sel ;
reg [7:0] o ;
(enb_ or sel)
if(enb_)
o = 8'b1111_1111 ;
else
case(sel)
3'b000 : o = 8'b1111_1110 ;
3'b001 : o = 8'b1111_1101 ;
3'b010 : o = 8'b1111_1011 ;
3'b011 : o = 8'b1111_0111 ;
3'b100 : o = 8'b1110_1111 ;
3'b101 : o = 8'b1101_1111 ;
3'b110 : o = 8'b1011_1111 ;
3'b111 : o = 8'b0111_1111 ;
default : o = 8'bx ;
endcase
endmodule
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46. Sequential Circuit Design
Outputs
Inputs
Combinational
circuit
Memory
elements
a feedback path
the state of the sequential circuits
the state transition
synchronous circuits
asynchronous circuits
Examples-D latch
D flip-flop
register
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47. D-Latch,flip-flop module latch (G, D, Q); input G, D; output Q; reg Q;
or D)
begin
if (G)
 Q <= D;
end
endmodule
                     
module dff(Q, D, Clk);
output Q;
input D, Clk;
reg Q;
wire D, Clk;
Clk)
Q = D;
endmodule
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48. JK Flip-Flop module jkff(J, K, clk, Q); input J, K, clk; output Q;
reg Q;
reg Qm;
clk)
if(J == 1 && K == 0)
Qm <= 1;
else if(J == 0 && K == 1)
Qm <= 0;
else if(J == 1 && K == 1)
Qm <= ~Qm;
assign Q <= Qm;
endmodule
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49. A counter which runs through counts 0, 1, 2, 4, 9, 10, 5, 6, 8, 7, 0, …
module CntSeq(clk, reset, state);
parameter n = 4;
input clk, reset;
output [n-1:0]state;
reg1:0]state;
[n- integer k; //
clk)
if(reset)
state = 0;
else begin
case (state)
4'b0000:state = 4'b0001; //0 -> 1
4'b0001:state = 4'b0010; //1 -> 2
4'b0010:state = 4'b0100; //2 -> 4
4'b0100:state = 4'b1001; //4 -> 9
4'b1001:state = 4'b1010; //9 -> 10
4'b1010:state = 4'b0101; //10-> 5
4'b0101:state = 4'b0110; //5 -> 6
4'b0110:state = 4'b1000; //6 -> 8
4'b1000:state = 4'b0111; //8 -> 7
default:state = 4'b0000;
endcase
end
endmodule
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