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Multi-Rate Digital Signal Processing

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Presentation on theme: "Multi-Rate Digital Signal Processing"— Presentation transcript:

1 Multi-Rate Digital Signal Processing

2 Introduction In single-rate DSP systems, all data is sampled at the same rate---no change of rate within the system. In multirate DSP systems, sample rates are changed (or are different) within the system Multirate can offer several advantages -reduced computational complexity -reduced transmission data rate.

3 Example: Audio sample rate conversion
recording studios use 192 kHz CD uses 44.1 kHz wideband speech coding using 16 kHz master from studio must be rate-converted by a factor /192

4 Decimation System (Down Sampling)
xd[n] x[n] M=3

5 Decimation System (Down Sampling)
xd[n] = x[nM], where M is an integer Xd(z) =Sn xd[n]z-n =(1/M)Sm=0,(M-1) X(z(1/M)e-jm2p/M) Xd(ejw) =(1/M)Sm=0,(M-1) X(ej(w-m2p)/M)

6 Decimation System (Down Sampling)
Xd(ejw) =(1/M)Sm=0,(M-1) X(ej(w-m2p)/M) X(ejw/M) X(ejw) M=3 p 2p 4p 6p 8p X(ej(w-2p)/M) 2p X(ej(w-4p)/M) 4p

7 Sampling Rate Reduction System
Low-pass filter with cutoff at p/M M yd[n] x[n] y[n]

8 Interpolation System (Up Sampling)
xu[n] x[n] L=3

9 Interpolation System (Up Sampling)
xu[n] = x[n/L], n = 0, ±L, ±2L, … 0, otherwise Xu(z) =Sn xu[n]z-n = X(zL) Xu(ejw) = X(ejwL)

10 Interpolation System (Up Sampling)
Xu(ejw) = X(ejwL) L=3 X(ejw) X(ejwL) 2p/3 4p/3 2p

11 Sampling Rate Increase System
Low-pass filter with cutoff at p/L xu[n] L y[n] x[n]

12 Decimation and Interpolation
x[n] y[n] M=3

13 Decimation and Interpolation
x[n] y[n] Let WM = e-j2p/M Y(z) = (1/M)Sm=0,(M-1) X(ze-jm2p/M) = (1/M)Sm=0,(M-1) X(zWMm) Y(ejw)= (1/M)Sm=0,(M-1) X(ej(w-m2p/M))

14 Decimation and Interpolation
Y(ejw)= (1/M)Sm=0,(M-1) X(ej(w-jm2p/M)) X(ejw) M=3 2p/3 2p X(ej(w-2p/M)) 2p/3 X(ej(w-4p/M)) 4p/3

15 Fractional Sampling Rate Change
Low-pass filter with cutoff at min(p/L,p/M) L M y[n] x[n]

16 Block Interconnection Identities
M C C M Multiply by a Constant M M M

17 Block Interconnection Identities
M M M

18 Block Interconnection Identities
L

19 Block Interconnection Identities

20 Multi-Rate Identities
H(zM) M M H(z) L H(zL) H(z) L

21 Multi-rate Switch Models
3 x[n] n = 0, 3, 6,… Z-1 3 n = -1, 2, 5,… Z-1 3 n = -2, 1, 4,…

22 Multi-rate Switch Models
3 Serial to Parallel Converter x[3n] x[n] Z-1 3 x[3n-1] x[n] Z-1 3 x[3n-2]

23 Multi-rate Switch Models
3 x1[n] n = 2, 5, 8,… Z-1 3 x2[n] n = 1, 4, 7,… Z-1 3 n = 0, 3, 6,… x3[n]

24 Multi-rate Switch Models
3 Parallel to Serial Converter x1[n] x[3n+2] Z-1 3 x[3n+1] x2[n] x[n] Z-1 3 x[3n] x3[n]

25 Poly-phase Structure of Decimation Filter
y[n] x[n] 3 H(z) y[3n] H(z) = D0(z3)+ z-1D1(z3)+z-2D2(z3) D0(z3) x[n] Z-1 y[n] 3 y[3n] D1(z3) Z-1 D2(z3)

26 Poly-phase Structure of Decimation Filter
H(z) = D0(z3)+ z-1D1(z3)+z-2D2(z3) 3 D0(z3) x[n] y[3n] Z-1 3 D1(z3) Z-1 3 D2(z3)

27 Poly-phase Structure of Decimation Filter
H(z) = D0(z3)+ z-1D1(z3)+z-2D2(z3) 3 D0(z) x[n] y[3n] Z-1 3 D1(z) Z-1 3 D2(z)

28 Poly-phase Structure of Decimation Filter
H(z) = D0(z3)+ z-1D1(z3)+z-2D2(z3) Serial to Parallel Converter D0(z) x[3n] y[3n] x[n] D1(z) x[3n-1] D2(z) x[3n-2]

29 Poly-phase Structure of Interpolation Filter
3 x[n] H(z) y[n] H(z) = z-2I0(z3)+ z-1I1(z3)+I2(z3) 3 I0(z3) Z-2 x[n] I1(z3) Z-1 y[n] I2(z3)

30 Poly-phase Structure of Interpolation Filter
H(z) = z-2I0(z3)+ z-1I1(z3)+I2(z3) 3 x[n] I0(z3) Z-1 3 I1(z3) Z-1 3 I2(z3) y[n]

31 Poly-phase Structure of Interpolation Filter
H(z) = z-2I0(z3)+ z-1I1(z3)+I2(z3) 3 x[n] I0(z) Z-1 3 I1(z) Z-1 3 I2(z) y[n]

32 Poly-phase Structure of Interpolation Filter
H(z) = z-2I0(z3)+ z-1I1(z3)+I2(z3) Parallel to Serial Converter x[n] I0(z) y[3n+2] I1(z) y[3n+1] y[n] I2(z) y[3n]

33 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 3 F0(z3) Z-2 x[n] 4 F1(z3) Z-1 y[n] F2(z3)

34 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 3 F0(z) Z-2 x[n] 4 3 F1(z) Z-1 y[n] 3 F2(z)

35 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 3 F0(z) Z6 Z-8 x[n] y[n] 4 3 F1(z) Z3 Z-4 3 F2(z)

36 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 3 4 F0(z) Z2 Z-2 x[n] y[n] 3 4 F1(z) Z1 Z-1 3 4 F2(z)

37 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 3 4 Z2 F0(z) Z-2 x[n] y[n] 3 4 Z1 F1(z) Z-1 3 4 F2(z)

38 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 4 3 Z2 F0(z) Z-2 x[n] y[n] 4 3 Z1 F1(z) Z-1 4 3 F2(z)

39 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) (M=4, L=3) 4 Parallel to Serial Converter x[n] Z2 F0(z) 4 y[n] Z1 F1(z) 4 F2(z)

40 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) Fk(z) = Fk0(z4)+ z-1Fk1(z4)+z-2Fk2(z4)+z-3Fk3(z4) (M=4, L=3) 4 Parallel to Serial Converter x[n] Z2 F0(z) 4 y[n] Z1 F1(z) 4 F2(z)

41 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) Fk(z) = Fk0(z4)+ z-1Fk1(z4)+z-2Fk2(z4)+z-3Fk3(z4) (M=4, L=3) Fk0 Serial to Parallel Converter Fk1 Parallel to Serial Converter x[n] Z2 Fk2 Fk3 y[n] 4 Z1 F1(z) 4 F2(z)

42 Poly-phase Structure of Fractional Sampling Rate Filter
H(z) = z-2F0(z3)+ z-1F1(z3)+F2(z3) Fk(z) = Fk0(z4)+ z-1Fk1(z4)+z-2Fk2(z4)+z-3Fk3(z4) (M=4, L=3) Fk0 Serial to Parallel Converter x[n] Fk1 Parallel to Serial Converter Z2 Fk2 Fk3 y[n] 4 Z-1 F1(z) 4 Z-1 F2(z)

43 Efficient Design for Very Narrow-band Filters
x[n] H(z) y[n] x[n] F(z) G(zM) y[n]

44 Efficient Design for Very Narrow-band Filters
p H(z) wp ws p G(z) Desired passband Mws Mwp Images G(zM) p wp ws 2p/M p F(z) wp 2p/M-ws

45 Efficient Design for Very Narrow-band Filters
M x[n] F(z) G(zM) y[n] M x[n] F(z) G(z) y[n] x[n] F0(z) M z-1 G(z) y[n] F1(z) M + z-1

46 Efficient Design for Very Narrow-band Filters
F0(z) Serial to Parallel Converter G(z) y[n] F1(z) + x[n] FM-1(z)

47 Multi-stage Decimation System
x[n] H(z) y[n] M1M2 x[n] F(z) G(zM1) y[n] M2 M1 y[n] x[n] F(z) G(z)

48 Multi-stage Decimation System
F0(z) G0(z) Serial to Parallel Converter Serial to Parallel Converter F1(z) G1(z) x[n] + + y[n] FM1 -1(z) GM2 -1(z)

49 Multi-stage Interpolation System
x[n] H(z) y[n] L1L2 x[n] G(zL1) F(z) y[n] L2 L1 y[n] x[n] G(z) F(z)

50 Multi-stage Interpolation System
G0(z) Parallel to Serial Converter F0(z) Parallel to Serial Converter G1(z) F1(z) x[n] y[n] GL2-1(z) FL1-1(z)

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