1. CSCI 312 Computer Organization and Architecture
MIPS
CSCI 312 Computer Organization and Architecture
Fall 2019
Lecture note
Dr. Sajedul Talukder

2. MIPS Architecture 32-bit RISC Processor 32 32-bit Registers, $0..$31
Pipelined Execution of Instructions
All instructions are 32-bits
Most Instructions executed in one clock cycle
bit memory words
Byte addressable memory
A 32-bit word contains four bytes
To address the next word of memory add 4

3. The University of Adelaide, School of Computer Science
Instruction Set
24 January 2020
The repertoire of instructions of a computer
Different computers have different instruction sets
But with many aspects in common
Early computers had very simple instruction sets
Simplified implementation
Many modern computers also have simple instruction sets
Chapter 2 — Instructions: Language of the Computer

4. The MIPS Instruction Set
The University of Adelaide, School of Computer Science
The MIPS Instruction Set
24 January 2020
Used as the example throughout the book
Stanford MIPS commercialized by MIPS Technologies (
Large share of embedded core market
Applications in consumer electronics, network/storage equipment, cameras, printers, …
Typical of many modern ISAs
See MIPS Reference Data tear-out card, and Appendixes B and E
Chapter 2 — Instructions: Language of the Computer

5. The University of Adelaide, School of Computer Science
24 January 2020
Registers
Chapter 2 — Instructions: Language of the Computer

6. $a0-$a3 $s0-$s7 $t0-$t9 $sp $ra
MIPS Register Names
MIPS register names begin with a $. There are two naming conventions:
By number:
$0 $1 $2 … $31
By (mostly) two-character names, such as:
$a0-$a3 $s0-$s7 $t0-$t9 $sp $ra
Not all of the registers are equivalent:
E.g., register $0 or $zero always contains the value 0
(go ahead, try to change it)
Other registers have special uses, by convention:
E.g., register $sp is used to hold the “stack pointer”
You have to be a little careful in picking registers for your programs.

7. MIPS Operands
MIPS is a register-to-register, or load/store, architecture.
The destination and sources must all be registers.
Special instructions, which we’ll see soon, are needed to access main memory.
MIPS uses three-address instructions for data manipulation.
Each ALU instruction contains a destination and two sources.
For example, an addition instruction (a = b + c) has the form:
operation
add a,
operands b, c
destination
sources

8. Register Operands Arithmetic instructions use register operands
In MIPS assembly language
$s0 - $s7 maps onto register 16 to 23
$t0 - $t7 maps onto register 8 to 15
$s0 means register 16
$s1 means register 17
…….
$t0 means register 8
$t1 means register 9
……..

9. Register Operand Example
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Register Operand Example
24 January 2020
C code:
f = (g + h) - (i + j);
f, …, j in $s0, …, $s4
Compiled MIPS code:
add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1
Chapter 2 — Instructions: Language of the Computer

10. Arithmetic Operations
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Arithmetic Operations
24 January 2020
The basic integer arithmetic operations include the following:
add sub mul div
Three operands
Two sources and one destination
add a, b, c # a gets b + c
All arithmetic operations have this form
Chapter 2 — Instructions: Language of the Computer

11. The University of Adelaide, School of Computer Science
Arithmetic Example
24 January 2020
C code:
f = (g + h) - (i + j);
Compiled MIPS code:
add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1
Be careful not to modify registers that are needed again later
Chapter 2 — Instructions: Language of the Computer

12. The University of Adelaide, School of Computer Science
Memory Operands
24 January 2020
Address
8-bit data
Word 1 Word 2 Word 3
Main memory used for composite data
Arrays, structures, dynamic data
To apply arithmetic operations
Load values from memory into registers
Store result from register to memory
Memory is byte addressed
Each address identifies an 8-bit byte
Words are aligned in memory
Address must be a multiple of 4
Chapter 2 — Instructions: Language of the Computer

13. Memory Operand Example 1
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Memory Operand Example 1
24 January 2020
C code:
g = h + A[8];
g in $s1, h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
4 bytes per word
lw $t0, 32($s3) # load word add $s1, $s2, $t0
offset
base register, i.e., rs
Chapter 2 — Instructions: Language of the Computer

14. Memory Operand Example 2
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Memory Operand Example 2
24 January 2020
C code:
A[12] = h + A[8];
h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word
Chapter 2 — Instructions: Language of the Computer

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Immediate Operands
24 January 2020
Constant data specified in an instruction
addi $s3, $s3, 4
No subtract immediate instruction
Just use a negative constant
addi $s2, $s1, -1
Design Principle 3: Make the common case fast
Small constants are common
Immediate operand avoids a load instruction
Chapter 2 — Instructions: Language of the Computer

16. The University of Adelaide, School of Computer Science
The Constant Zero
24 January 2020
MIPS register $0 ($zero) is the constant 0
Cannot be overwritten
Useful for common operations
E.g., move between registers
add $t2, $s1, $zero
Chapter 2 — Instructions: Language of the Computer

17. Loading and storing bytes
The MIPS instruction set includes dedicated load and store instructions for accessing memory
The main difference is that MIPS uses indexed addressing.
The address operand specifies a signed constant and a register.
These values are added to generate the effective address.
The MIPS - load byte instruction lb transfers one byte of data from main memory to a register.
lb $t0, 20($a0) # $t0 = Memory[$a0 + 20]
The store byte instruction sb transfers the lowest byte of data from a register into main memory.
sb $t0, 20($a0) # Memory[$a0 + 20] = $t0

18. Loading and storing words
You can also load or store 32-bit quantities—a complete word instead of
just a byte—with the lw and sw instructions.
lw $t0, 20($a0) sw $t0, 20($a0)
# $t0 = Memory[$a0 + 20] # Memory[$a0 + 20] = $t0
Most programming languages support several 32-bit data types.
Integers
Single-precision floating-point numbers
Memory addresses, or pointers
Unless otherwise stated, we’ll assume words are the basic unit of data.

19. MIPS Labels
Instead of absolute memory addresses symbolic labels are used to indicate memory addresses in assembly language
Assembly Language Programs are easier to modify and are easier to understand when labels are used
Examples
Variable X is stored a location 123 in memory - Use label X instead of 123 in programs.
Location LOOP_TOP is address 250 in a program - Use label LOOP_TOP instead of jump address 250 in programs

20. MIPS Example: A = B + C; LW $2, B ;Register 2 = value of B
LW $3, C ;Register 3 = value of C
ADD $4, $2, $3 ;Register 4 = B+C
SW $4, A ; A = B + C

21. MIPS Assembler Directives
Assembler directives are commands for the assembler that do not generate machine instructions
Assembler directives are also called pseudo ops
Used to set up data and instruction areas

22. MIPS Assembler Directive Examples
.DATA
The following lines are constant or data values
.WORD
Reserve a 32-bit word in memory for a variable
.ASCII
Place a string in memory using the ASCII character code
.TEXT
The following lines are instructions

23. MIPS Assembly Language Label Examples
N: .WORD 0
Like declaring an Integer, N, in a HLL
Sets up N as a Label that points to a 32-bit data value
Initial value is set to 0
LOOP: ADD $a0,$a0,$a1
Sets up LOOP as a Label that points to the Add instruction
Can jump to LOOP (i.e. J LOOP)

24. Pseudo-instructions
MIPS assemblers support pseudo-instructions that give the illusion of a more expressive instruction set, but are actually translated into one or more simpler, “real” instructions.
For example, you can use the li and move pseudo-instructions:
li $a0, move $a1, $t0
# Load immediate 2000 into $a0 # Copy $t0 into $a1
They are probably clearer than their corresponding MIPS instructions:
addi $a0, $0, add $a1, $t0, $0
# Initialize $a0 to # Copy $t0 into $a1
We’ll see lots more pseudo-instructions this semester.
Unless otherwise stated, you can always use pseudo-instructions in your assignments and on exams.

25. MIPS Assembly Language Examples
ADD $1,$2,$3
Register 1 = Register 2 + Register 3
SUB $1,$2,$3
Register 1 = Register 2 - Register 3
AND $1,$2,$3
Register 1 = Register 2 AND Register 3
ADDI $1,$2,10
Register 1 = Register
SLL $1, $2, 10
Register 1 = Register 2 shifted left 10 bits

26. MIPS Assembly Language Examples
LW $1,100
Register 1 = Contents of memory location 100
Used to load registers
SW $1,100
Contents of memory location 100 = Register 1
Used to save registers
LUI $1,100
Register 1 upper 16-bits = 100
Lower 16-bits are set to all 0’s
Used to load a constant in the upper 16-bits
Other constants in instructions are only 16-bits, so this instruction is used when a constant larger than 16-bits is required for the operation

27. MIPS Assembly Language Examples
J 100
Jumps to PC+100
JAL 100
Save PC in $31 and Jumps to PC+100
Used for subroutine calls
JR $31
Jumps to address in register 31
Used for subroutine returns

28. MIPS Assembly Language Examples
BEQ $1, $2, 100
If register 1 equal to register 2 jump to PC+100
Used for Assembly Language If statements
BNE $1, $2, 100
If register 1 not equal to register 2 jump to PC+100

29. MIPS Assembly Language Examples
SLT $1,$2,$3
If register 2 is less than register 3 then register 1=1 else register 1=0
In an assembly language flag a “1” means true and a “0” means false
Used in conjunction with BEQ/BNE instruction to implement any arithmetic comparison
Required for more complex assembly language If statements

30. Memory alignment
Keep in mind that memory is byte-addressable, so a 32-bit word actually
occupies four contiguous locations (bytes) of main memory.
Address
8-bit data
Word 1 Word 2 Word 3
The MIPS architecture requires words to be aligned in memory; 32-bit words must start at an address that is divisible by 4.
0, 4, 8 and 12 are valid word addresses.
1, 2, 3, 5, 6, 7, 9, 10 and 11 are not valid word addresses.
Unaligned memory accesses result in a bus error, which you may have unfortunately seen before.
This restriction has relatively little effect on high-level languages and compilers, but it makes things easier and faster for the processor.

31. Memory alignment MIPS is Big Endian
Keep in mind that memory is byte-addressable, so a 32-bit word actually
occupies four contiguous locations (bytes) of main memory.
Address
8-bit data
Word 1 Word 2 Word 3
MIPS is Big Endian
Most-significant byte at lowest address of a word
Big here means the largest address, the least significant byte at the largest address. Byte address The MSB at address 0, the LSB at address 3
Little Endian:
least-significant byte at lowest address
Little here means the least address. The least significant byte at the least address. Byte Address MSB at address 3, the LSB at address 0

32. An array of words
Remember to be careful with memory addresses when accessing words.
For instance, assume an array of words begins at address 2000.
The first array element is at address 2000.
The second word is at address 2004, not 2001.
Example, if $a0 contains 2000, then
lw $t0, 0($a0)
accesses the first word of the array, but
lw $t0, 8($a0)
would access the third word of the array, at address 2008.

33. Loops for (i = 0; i < 4; i++) { // stuff } Loop: j Loop # goto Loop
add $t0, $zero, $zero
// stuff
# i is initialized to 0, $t0 = 0
Loop:
addi
$t0,
$t0, 1 #
i ++
slti
$t1,
$t0, 4
$t1 = 1 if i < 4
bne
$zero,
Loop
go to Loop if i < 4

34. Translating an if-then-else statements
If there is an else clause, it is the target of the conditional branch
— And the then clause needs a jump over the else clause
// increase the magnitude of v0 by one
if (v0 < 0)
v0 --;
else
v0 ++;
v1 = v0;
bge $v0, $0, E sub $v0, $v0, 1 j L
E: add $v0, $v0, 1 L: move $v1, $v0
— Drawing the control-flow graph can help you out.

35. An Example Function: Factorial
int fact(int n) {
fact:
li $t0, 1 move $t1,$a0
int i, f = 1;
for (i = n; i > 0; i--) f = f * i;
return f;
# set i to n
loop:
blez $t1,exit # exit if done mul $t0,$t0,$t1 # build factorial addi $t1, $t1,-1 # i--
j loop }
exit:
move $v0,$t0

36. Control-flow Example
Let’s write a program to count how many bits are set in a 32-bit word.
int count = 0;
for (int i = 0 ; i < 32 ; i ++) { int bit = input & 1;
if (bit != 0) { count ++; }
input = input >> 1;
.text
main: li
$a0, 0x1234
## input = 0x1234
$t0, 0
## int count = 0;
$t1, 0
## for (int i = 0
main_loop:
bge
$t1, 32, main_exit
## exit loop if i >= 32
andi
$t2, $a0, 1
## bit = input & 1
beq
$t2, $0, main_skip
## skip if bit == 0
addi
$t0, $t0, 1
## count ++
main_skip:
srl
$a0, $a0, 1
## input = input >> 1
add
$t1, $t1, 1
## i ++ j
main_loop
main_exit: jr
$ra

37. Functions in MIPS
We’ll talk about the 3 steps in handling function calls:
The program’s flow of control must be changed.
Arguments and return values are passed back and forth.
Local variables can be allocated and destroyed.
And how they are handled in MIPS:
New instructions for calling functions.
Conventions for sharing registers between functions.
Use of a stack.

38. Control flow in C
Invoking a function changes the control flow of a program twice.
Calling the function
Returning from the function
In this example the main function calls fact twice, and fact returns twice—but to different locations in main.
Each time fact is called, the CPU has to remember the appropriate return address.
Notice that main itself is also a function! It is called by the operating system when you run the program.
int main() {
...
t1 = fact(8); t2 = fact(3); t3 = t1 + t2;
... }
int fact(int n) {
int i,
for (i
f =
f = 1;
= n; i > 1; i--)
f * i; f;
return }

39. Control flow in MIPS
MIPS uses the jump-and-link instruction jal to call functions.
The jal saves the return address (the address of the next instruction) in the dedicated register $ra, before jumping to the function.
jal is the only MIPS instruction that can access the value of the program counter, so it can store the return address PC+4 in $ra.
jal Fact
To transfer control back to the caller, the function just has to jump to the address that was stored in $ra.
jr $ra
Let’s now add the jal and jr instructions that are necessary for our factorial example.

40. Data flow in MIPS
MIPS uses the following conventions for function arguments and results.
Up to four function arguments can be “passed” by placing them in argument registers $a0-$a3 before calling the function with jal.
A function can “return” up to two values by placing them in registers
$v0-$v1, before returning via jr.
These conventions are not enforced by the hardware or assembler, but programmers agree to them so functions written by different people can interface with each other.
Later we’ll talk about handling additional arguments or return values.

41. Nested function calls
Notice function calls and returns occur in a LIFO order: the most recently called function is the first one to return. 1
A: ...
jal B 6
A2: ...
jr $ra 2
Someone calls A
A calls B
B calls C
C returns to B
B returns to A
A returns 5
B: ...
jal C
B2: ...
jr $ra 3 4
Here, for example, C must return to B
before B can return to A.
C: ...
jr $ra

42. The big problem so far: Nested functions
A problematic situation happens when you call a function that then calls another function.
Let’s say A calls B, which calls C.
The arguments for the call to C would be placed in $a0-$a3, thus overwriting the original arguments for B.
Similarly, jal C overwrites the return address that was saved in $ra by the earlier jal B.
A: ...
# Put B’s jal B
A2: ...
args in $a0-$a3 # $ra = A2
B: ...
# Put C’s # erasing
args in $a0-$a3, B’s args!
# $ra = B2
jal C
B2: ...
jr $ra
# Where does # this go???
C: ...
jr $ra

43. Spilling registers
The CPU has a limited number of registers for use by all functions, and it’s possible that several functions will need the same registers.
We can keep important registers from being overwritten by a function call, by saving them before the function executes, and restoring them after the function completes.
But there are two important questions.
Who is responsible for saving registers—the caller or the callee?
Where exactly are the register contents saved?

44. Who saves the registers?
Who is responsible for saving important registers across function calls?
The caller knows which registers are important to it and should be saved.
The callee knows exactly which registers it will use and potentially overwrite.
However, in the typical “black box” programming approach, the caller and callee do not know anything about each other’s implementation.
Different functions may be written by different people or companies.
A function should be able to interface with any client, and different implementations of the same function should be substitutable.
So how can two functions cooperate and share registers when they don’t know anything about each other?

45. The caller could save the registers…
One possibility is for the caller to save any important registers that it needs before making a function call, and to restore them after.
But the caller does not know what registers are actually written by the callee function, so it may save more registers than necessary.
In the example on the right, frodo wants to preserve $a0, $a1, $s0 and $s1 from gollum, but gollum may not even use those registers.
frodo: li
$a0, 3 li
$a1, 1
$s0, 4
$s1,
# Save registers
# $a0, $a1, $s0, $s1
jal gollum
# Restore registers # $a0, $a1, $s0, $s1
add $v0, $a0, $a1 add $v1, $s0, $s1 jr $ra

46. …or the callee could save the registers…
Another possibility is if the callee saves and restores any registers it might overwrite.
For instance, a gollum function that uses registers $a0, $a2, $s0 and $s2 could save the original values first, and restore them before returning.
But the callee does not know what registers are important to the caller, so again it may save more registers than necessary.
gollum:
# Save registers # $a0 $a2 $s0 $s2
li $a0, 2
li $a2, 7
li $s0, 1
li $s2, 8
...
# Restore registers # $a0 $a2 $s0 $s2
jr $ra

47. …or they could work together
MIPS uses conventions again to split the register spilling chores.
The caller is responsible for saving and restoring any of the following caller-saved registers that it cares about.
$t0-$t9 $a0-$a3 $v0-$v1
In other words, the callee may freely modify these registers, under the assumption that the caller already saved them if necessary.
The callee is responsible for saving and restoring any of the following callee-saved registers that it uses. (Remember that $ra is “used” by jal.)
$s0-$s7 $ra
Thus the caller may assume these registers are not changed by the callee.
— $ra is tricky; it is saved by a callee who is also a caller.
Be especially careful when writing nested functions, which act as both a caller and a callee!

48. Register spilling example
This convention ensures that the caller and callee together save all of the important registers—frodo only needs to save registers $a0 and $a1, while gollum only has to save registers $s0 and $s2.
frodo: li
li li li
$a0, 3
$a1, 1
$s0, 4
$s1, 1
gollum:
# Save registers # $s0 and $s2
li li li li
...
$a0, 2
$a2, 7
$s0, 1
$s2, 8
# Save registers
# $a0 and $a1
jal gollum
# Restore registers # $a0 and $a1
# Restore registers # $s0 and $s2
jr $ra
add $v0, $a0, $a1 add $v1, $s0, $s1 jr $ra

49. Where are the registers saved?
Now we know who is responsible for saving which registers, but we still need to discuss where those registers are saved.
It would be nice if each function call had its own private memory area.
This would prevent other function calls from overwriting our saved registers—otherwise using memory is no better than using registers.
We could use this private memory for other purposes too, like storing local variables.

50. Stacks and function calls
It’s natural to use a stack for function call storage. A block of stack space, called a stack frame, can be allocated for each function call.
When a function is called, it creates a new frame onto the stack, which will be used for local storage.
Before the function returns, it must pop its stack frame, to restore the stack to its original state.
The stack frame can be used for several purposes.
Caller- and callee-save registers can be put in the stack.
The stack frame can also hold local variables, or extra arguments and return values.

51. The MIPS stack
0x7FFFFFFF
stack
In MIPS machines, part of main memory is reserved for a stack.
The stack grows downward in terms of memory addresses.
The address of the top element of the stack is stored (by convention) in the “stack pointer” register, $sp.
MIPS does not provide “push” and “pop” instructions. Instead, they must be done explicitly by the programmer. 0x

52. Pushing elements To push elements onto the stack:
Move the stack pointer $sp down to make room for the new data.
Store the elements into the stack.
For example, to push registers $t1 and $t2 onto the stack:
word 1
word 2
$sp
sub
$sp,
$sp, 8 sw
$t1,
4($sp)
$t2,
0($sp)
Before
word 1
word 2
$t1
$t2
An equivalent sequence is: sw
$t1,
-4($sp)
$t2,
-8($sp)
sub
$sp,
$sp, 8
$sp
Before and after diagrams of the stack are shown on the right.
After

53. Accessing and popping elements
You can access any element in the stack (not just the top one) if you know where it is relative to $sp.
For example, to retrieve the value of $t1:
lw $s0, 4($sp)
You can pop, or “erase,” elements simply by adjusting the stack pointer upwards.
To pop the value of $t2, yielding the stack shown at the bottom:
word 1
word 2
$t1
$t2
$sp
word 1
word 2
$t1
$t2
addi $sp, $sp, 4
Note that the popped data is still present in memory, but data past the stack pointer is considered invalid.
$sp

54. Summary Today we focused on implementing function calls in MIPS.
We call functions using jal, passing arguments in registers $a0-$a3.
Functions place results in $v0-$v1 and return using jr $ra.
Managing resources is an important part of function calls.
To keep important data from being overwritten, registers are saved according to conventions for caller-save and callee-save registers.
Each function call uses stack memory for saving registers, storing local variables and passing extra arguments and return values.
Assembly programmers must follow many conventions. Nothing prevents a rogue program from overwriting registers or stack memory used by some other function.

55. Machine language
Machine language, the binary representation for instructions.
We’ll see how it is designed for the common case
Fixed-sized (32-bit) instructions
Only 3 instruction formats
Limited-sized immediate fields

56. Assembly vs. machine language
So far we’ve been using assembly language.
We assign names to operations (e.g., add) and operands (e.g., $t0).
Branches and jumps use labels instead of actual addresses.
Assemblers support many pseudo-instructions.
Programs must eventually be translated into machine language, a binary format that can be stored in memory and decoded by the CPU.
MIPS machine language is designed to be easy to decode.
Each MIPS instruction is the same length, 32 bits.
There are only three different instruction formats, which are very similar to each other.
Studying MIPS machine language will also reveal some restrictions in the
instruction set architecture, and how they can be overcome.

57. R-type format op rs rt rd shamt func 6 bits 5 bits
Register-to-register arithmetic instructions use the R-type format. op rs rt rd
shamt
func
6 bits
5 bits
This format includes six different fields.
op is an operation code or opcode that selects a specific operation.
rs and rt are the first and second source registers.
rd is the destination register.
shamt is only used for shift instructions.
func is used together with op to select an arithmetic instruction.
The inside back cover of the textbook lists opcodes and function codes for all of the MIPS instructions.

58. About the registers
We have to encode register names as 5-bit numbers from to
For example, $t8 is register $24, which is represented as
The complete mapping is given on page A-23 in the book.
The number of registers available affects the instruction length.
Each R-type instruction references 3 registers, which requires a total of 15 bits in the instruction word.
We can’t add more registers without either making instructions longer than 32 bits, or shortening other fields like op and possibly reducing the number of available operations.

59. R-type conversion
Complete list:

60. R-type conversion example
a = b + c
assembly code:
add $s0, $s1, $s2    # add rd, rs, rt
machine code:
(op rs rt rd shamt funct)

61. I-type format op rs rt address 6 bits 5 bits 16 bits
Load, store, branch and immediate instructions all use the I-type format. op rs rt
address
6 bits
5 bits
16 bits
For uniformity, op, rs and rt are in the same positions as in the R-format.
The meaning of the register fields depends on the exact instruction.
rs is a source register—an address for loads and stores, or an operand for branch and immediate arithmetic instructions.
rt is a source register for branches, but a destination register for the other I-type instructions.
The address is a 16-bit signed two’s-complement value.
It can range from -32,768 to +32,767.
But that’s not always enough!

62. I-type conversion

63. I-type conversion example
lw $t0, 32($s3) (registers 8 and 19)

64. Larger constants
Larger constants can be loaded into a register 16 bits at a time.
The load upper immediate instruction lui loads the highest 16 bits of a
register with a constant, and clears the lowest 16 bits to 0s.
An immediate logical OR, ori, then sets the lower 16 bits.
To load the 32-bit value :
lui $s0, 0x003D
ori $s0, $s0, 0x0900
# $s0 = 003D 0000 (in hex)
# $s0 = 003D 0900
This illustrates the principle of making the common case fast.
Most of the time, 16-bit constants are enough.
It’s still possible to load 32-bit constants, but at the cost of two instructions and one temporary register.
Pseudo-instructions may contain large constants. Assemblers including SPIM will translate such instructions correctly.

65. Conditional branch instructions
Beq $t0,$t1, label I:
I-type instruction op rs rt
address/immediate
op 6 bits
rs 5 bits
rt 5 bits
code for the comparison to perform 1st argument register
2nd argument register
imm 16 bits jump offset embedded in instruction 32 bits

66. Calculating the jump offset
Number of instructions from the next instruction
(nop is an instruction that does nothing)
beq$t0,$t1, skip nop#0(starthere) nop#1
nop#2
skip:nop#3!
...
loop:nop#-5
nop#-4 nop#-3 nop#-2
beq$t0,$t1, loop
nop#0(starthere)
offset = 3
offset = -5

67. Assembling a conditional branch instruction
beq $t0,$t1, label nop
nop
label: nop op rs rt
address/immediate
op = 4
rs = 8
rt = 9
imm = 2
(look up op code for beq) ($t0 = $8)
($t1 = $9) (jump offset) 4 8 9 2
000100
01000
01001
0000
0010 0x

68. Exercises R: I: Assemble the following program: Name Number 2–3 4–7
$zero
$v0–$v1
2–3
$a0–$a3
4–7
$t0–$t7
8–15
$s0–$s7
16–23
$t8–$t9
24–25
$sp 29
$ra 31 R: I:
Assemble the following program:
#Pseudocode: #do{
#i++
#}while(i!=j);
loop: addi $s0,$s0, 1
Bne $s0,$s1, loop rs rt rd sh fn op rs rt
addr/imm
Instr op
addi 8
beq 4
bne 5

69. Larger branch constants
Empirical studies of real programs show that most branches go to targets less than 32,767 instructions away—branches are mostly used in loops and conditionals, and programmers are taught to make code bodies short.
If you do need to branch further, you can use a jump with a branch. For example, if “Far” is very far away, then the effect of:
beq $s0, $s1, Far
...
can be simulated with the following actual code.
bne $s0, $s1, Next j Far
...
Next:
Again, the MIPS designers have taken care of the common case first.

70. J-type format op address 6 bits 26 bits
Finally, the jump instruction uses the J-type instruction format. op
address
6 bits
26 bits
The jump instruction contains a word address, not an offset
Remember that each MIPS instruction is one word long, and word addresses must be divisible by four.
So instead of saying “jump to address 4000,” it’s enough to just say “jump to instruction 1000.”
A 26-bit address field lets you jump to any address from 0 to 228.
your MP solutions had better be smaller than 256MB
For even longer jumps, the jump register, or jr, instruction can be used.
jr $ra # Jump to 32-bit address in register $ra

71. J-type conversion

72. J-type conversion example
j LOOP
The address stored in a j instruction is 26 bits of the address associated with the specified label. The 26 bits are achieved by dropping the high-order 4 bits of the address and the low-order 2 bits (which would always be 00, since addresses are always divisible by 4).
address = low-order 26 bits of (addrFromLabelTable/4)
In the example above, if LOOP is at address 1028, then the value stored in the machine instruction would be 257.

73. Putting everything together
Assembly Code:
add $s0, $s1, $s2    # add $16,$17,$18
lw $t0, 32($s3) # registers $8 and $19
j LOOP # jump to address 1028
Machine Code:
Op rs rt rd shamt funct

74. Assembly language vs. machine code
Assembler translates assembly code to machine code
loop: lw $t3, 0($t0) lw $t4, 4($t0) add $t2, $t3, $t4 sw $t2, 8($t0) addi $t0, $t0, 4 addi $t1, $t1, -1 bgtz $t1, loop
0x8d0b0000
0x8d0c0004
0x016c5020
0xad0a0008 0x
0x2129ffff
0x1d20fff9
Assembler
Assembly program (text file)
source code
Machine code (binary)
object code

75. How does the assembler assemble?
loop: lw $t3, 0($t0) lw $t4, 4($t0) add $t2, $t3, $t4 sw $t2, 8($t0) addi $t0, $t0, 4 addi $t1, $t1, -1 bgtz $t1, loop
0x8d0b0000
0x8d0c0004
0x016c5020
0xad0a0008 0x
0x2129ffff
0x1d20fff9
Assembler
Assembly program (text file)
source code
Machine code (binary)
object code

76. Assembling instructions
Assemble: translate from assembly to machine code
for our purposes: translate to a hex representation of the machine code
How to assemble a single instruction
1.decide which instruction format it is (R, I, J) 2.determine value of each component 3.convert to binary
4.convert to hexadecimal

77. Summary of Machine Language
MIPS machine language is designed to simplify processor
implementation
Fixed length instructions
3 instruction encodings: R-type, I-type, and J-type
Common operations fit in 1 instruction
Uncommon (e.g., long immediates) require more than one
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits = 32 bits
R I J
000000 rs rt rd
shamt
funct op
address/immediate
target address
Register-type
Immediate-type
Jump-type

78. Questions?
With this I would like to conclude my presentation. Thank you for attending my presentation. I would love to answer if you have any question.