1. Hardware Basic & Verilog Introduction
Speaker :呂宏璋(Hung-Chang Lu)
Date : 2019/07/18
Graduate Institute of Electronics Engineering
National Taiwan University

2. HDL vs Software Language
Verilog
System Verilog
VHDL
Hardware Description Language
C/C++
Python
Java
Software Language

3. HDL vs Software Language
Hardware
Software
Every part functions at the same time.
Line by line.

4. Circuit Abstraction Levels of Abstraction
RTL
Gate Level
Behavioral Representation(Architecture/System/Algorithmic Level) 這是Verilog中最高層次，在這個層次中我們會依據系統需求，來考慮模組或函式的功能而不去考慮硬體方面詳細的電路是如何運作的。所以會專注在系統架構或演算法的實現，因此在這個階段設計工作就會像在寫C。通常在此層次中所做的是用來模擬並且多半無法合成的，也無法看出電路特性。
Functional Representation(RTL/Dataflow Level) 在這個層次中，我們必需要指定資料處理的方式，明確的說明資料如何在暫存器及模組間儲存與傳送的流程。在此層次中可看出電路特性。
Structural Representation(Gate Level) 這個層次中的模組是由邏輯閘連接而成，所以設計的工作就會像以前用描繪邏輯閘來設計線路一樣，所以可以了解實際的硬體線路，但無法很快速的了解高階的行為。在這個層次中我們可以用內建的verilog原生元件來設計，不過由於在不同的製程下，各種的邏輯閘大小、延遲時間等等，也會跟著有所不同，所以此層次通常交由工具程式下去產生。
Physical Representation(Switch/Transistor Level) 這是Verilog最低階的層次，線路是由開關與儲存點組合而成。在此層次設計時必需清楚知道電晶體的元件特性，但此處寫出的Verilog是無法合成的。

5. Cell-Based IC Design Specifications RTL Coding Synthesis DFT Insertion
RTL code
Front-End
Synthesis
Gate-level netlist
DFT Insertion
ATPG
DFT(Design For testability) Insertion : 插入額外的邏輯去增加電路內部某些node的testability。
ATPG(Auto Test Patterns Generator)
Place and Route
Test Patterns
DRC LVS
GDS Layout
Back-End
Layout
Tape Out

6. RTL vs Gate-Level
RTL
Gate Level 1
in2
in1
out
sel

7. Combinational & Sequential
Sequential Part
Combinational Part
Sequential Part
in1
clk 1
sel
clk
out
in2
clk
Memory-less
Always running
Memory
Clock-triggered

8. Critical Path
Critical path is the path that has longest delay between reg or in/out in the whole circuit.
Delay: 5ns
clk
Delay: 3ns

9. Setup time & Hold time
Setup time( T su ) : the minimum amount of time the data signal should be held steady before the clock.
Hold time ( T h ) : the minimum amount of time the data signal should be held steady after the clock

10. Overview

11. Module Declaration Basic format Vector port is valid Example
But array is invalid
Use SystemVerilog
Example
module <module name> ( <port list> );
input <signal A> ;
output <signal B> ;
inout <signal C> ; ….
endmodule
down
counter
clk
rst
num 4

12. Parameter Parameters are constant.
Usually for states, width, height, etc.

13. Data type Frequently used data type are “wire” and “reg” Basic format
Example
wire [vector length] < variable name> [array size] ;
reg [vector length] < variable name> [array size] ;

14. Data type The datatype isn’t equal to the real circuit.
reg doesn’t mean a register. It depends on how you use these variables.
The selection of data type depends on the style of assignment
wire
for continuous assignment (assign)
reg
for procedural assignment (within always block)
Flip-Flop must be the data type of “reg”

15. Numeric System Number representation:
4’d9 : means 4 bits decimal 9 (4’b1001 in binary)
10’b01: means 10 bits binary 00_0000_0001
8’h10 : means 8 bits hexadecimal 10 (8’b0001_0000 in binary)
default value is decimal if there is no specific radix type and 32 bits.
Verilog support bitwise assignment:
<number of bits>’ <radix type> <value>
Value can include z and x
<signal A> = f( < signal B> [N:M] ) ; // only used some bits
<signal A> [ N:M] = <function value> // only assign some bits
A = 8’d12; A:
B = 8’h34;
A[7:4] = B[3:0]; B: 1 1 1

16. Unsigned and signed number
3’b001 1
3’b010 2
3’b011 3
3’b100 4 -4
3’b101 5 -3
3’b110 6 -2
3’b111 7 -1

17. Unsigned and signed number
In verilog, unsigned number is default.
If any of the input is unsigned, the operation is unsigned
To use signed number

18. Naming Rule Consistent naming convention for the design
Lowercase letters for signal names: reset, adder_tmp
Uppercase letters for constants: LOAD, STORE
clk sub-string for clocks: clk_blk1, clk_blk2, blk3_clk
rst sub-string for resets: rst_uart, ip_rst,
Suffix
_n for active-low, _z for tri-state, _a for async , …
state for current state, n_state for next state
Identical(similar) names for connected signals and ports

19. Assignment Describing the combinational circuit has two style:
Continuous assignment( assign)
Procedural assignment( always block)
Continuous assignment
Signal at left hand side(LHS) must be wire data type
Signal/ function value at RHS can be wire or reg data type
Combinational circuits are memory-less
assign <signal A> = <function value> ;

20. Always Block always @ (sensitivity list) Procedural assignment
<signal A> = <function value>;
Procedural assignment
Signal at LHS must be reg datatype
Signal at RHS can be reg or wire
If there are 2 or more statements in always block, remember to add “begin” and “end”
All signal in RHS must include in sensitivity list. (or use ”＊”) +
inA
inB C
1’b1 D

21. Assignment vs always block
LHS should be wire
LHS should be reg
RHS can be wire or reg
Begin & end are not allowed
Begin & end are used for multiple statements
Always running
Triggered by sensitivity lists
Combinational only
Could be sequential or combinational
Only 1-line conditional statement is allowed
1-line, if-else and case conditional statements are allowed.

22. Conditional Statement
For continuous assignment
You can’t use if-else or case statement in continuous assignment statement.
assign signal A = ( condition) ? (True Signal) : (False Signal) ; X

23. Conditional Statement
For procedural assignment
case ( target )
condition1: statement1 ;
condition2: statement2 ; …
default: statement N;
endcase
※ Remember write all possible case or use default.
※ The incomplete case will cause a Latch after synthesis.
※Remember that “If “must accompany with a “else”; otherwise, it cause a Latch too.
if ( condition1 )
statement1 ;
else if ( condition2 )
statement2 ;
else
statement3 ;

24. Value logic system - zero, false, low 1 - one, true, high Z
- zero, false, low 1
- one, true, high Z
- high impedance, float X
- unknown

25. Operators Common used operators
red word means has a limited synthesis support
Orange word means not recommended
Type
Operators
Examples
Arithmetic
+, -, *, /, %
A = B+C;
1001 =
Bitwise
~, &, |, ^, ~^
A = B^C;
0101 = 0111^ 0010
Reduction
&, ~&, |, ~|, ^, ~^
&A
0 = &(0111)
Logical
!=, ==, &&, ||, ===, !==
A == B
0 = (0111 == 0101)
Relational
>, >=, <, <=
A>B
1 = (0111 > 0101)
Shift
>>, <<
A= B << 1;
1110 = 0111 << 1
Conditional
(condition) ? s1: s2;
A = (B)? C: D;
0 = (0)? 1: 0;
Concatenation
{ }
A = {B, C}
0110 = {01, 10}
^ : XOR
Note : {b,3{a,b}} = {b, a, b, a, b, a, b}

26. For loop Auto unroll, can only use in always block
Different with C/C++
Provide a convenient way of writing a series of statement
Loop index variables must be integer
Example
integer k;
begin
out[0] = a[0]&b[0];
out[1] = a[1]&b[1];
out[2] = a[2]&b[2];
end
for (k=0;k<=2;k=k+1)
begin
out[k] = a[k]&b[k];

27. Generate For For continuous assignment / instance duplication
In Verilog-2001
Use genvar instead of integer
Block name is essential
Example:

28. Sequential Part
Verilog uses always block to generate flip-flop circuit.

29. Sequential Part Describe the behavior of sequential circuit
( <sensitivity edge > <clock> [or <sensitivity edge> < reset >] )
if ( reset ) … ; // reset mode
else … ; // normal mode
Asynchronous reset Synchronous reset
rst
D Q
next_count
count
clk

30. Syn & Asyn Reset
Difference between asynchronous reset and synchronous reset
Asyn
reset
Syn
reset at the posedge of reset signal
reset at the posedge of clock signal
no reset occurs

31. Blocking and Non blocking Assignment

32. Sequential Part
The circuit must have a reset signal. Otherwise, the initial value of Flip-Flop will be unknown.
Asynchronous or synchronous reset type depends on the circuit’s spec.
non-blocking assignment “ <=“ for sequential circuit.
Update value at the end of the always block
blocking assignment “=“ for combinational circuit.
blocking assignment
non-blocking assignment

33. Two Different Coding Style
Split into 2 parts
Merge into 1 part

34. Writing Next Logic Naming rule: XXX_next, XXX_n, n_XXX, next_XXX
Datatype: could be reg or wire.
wire
reg
Remember to have default value for conditional statement

35. Completeness of condition statement
You should assign all conditions clearly.
Wrong!
Correct!
reg [1:0]n_c,c;
clk) begin
c <= n_c;
end
begin
if (XXX)
begin
if(XXX)
n_c = 2’b00;
else
n_c = 2’b11;
reg [1:0]n_c,c;
clk) begin
c <= n_c;
end
begin
if (XXX)
begin
if(xxx)
n_c = 2’b00;
else
n_c = 2’b11;
n_c = c;
Latch!!!

36. Completeness of condition statement
Convenient way to save coding times.
To assign value for register in the beginning.
reg [1:0]n_c,c;
clk) begin
c <= n_c;
end
begin
n_c = c;
if (XXX)
begin
if(XXX)
n_c = 2’b00;
else
n_c = 2’b11;

37. Common issues
Data type “reg” is NOT definitely to be a register. Instead, the synthesis result depends on the described behavior of RTL.
Multiple Driven Signals issue
The variable of data type “wire” can NOT be repeatedly assigned.
The variable of data type “reg” can only be assigned in single always block. x x

38. Common issues Avoid appearance of Latch during synthesis.
Latch is too advanced for beginner of digital circuit.
Latch is due to incomplete assignment in combinational part.
Incomplete assignment implies that circuit will hold the previous value.
Usage of positive & negative clock simultaneously is NOT recommended.
Timing issue will cause the poor performance if not design properly.
Complicated clock tree for skew issue during place and route.

39. Good Verilog Code Clear Control Readability Performance
Maintainability

40. Clear Control
Circuit
Controlling Unit
Processing Unit

41. Finite State Machine (FSM)
Model of computation consisting of
A set (of finite number) of states
An initial state
Input symbols
Transition function that maps input symbols and current states to a next state
簡單的來說，有限狀態機是由一組狀態、一個起始狀態、 輸入、將輸入與現在狀態轉換為下一個狀態的轉換函數所組成。

42. FSM
parameter <MACRO> = <replaced number> ;
State parameter
IDLE
DOWN
ZERO
down =1
count=0

43. Readability Naming rule is important. Indent
Try to give a specific name rather than a,b,c…
Indent

44. Maintainability Make identical code to have single source
Single source coding
Multi source coding

45. Performance
Depending on the spec, different evaluation method may be used.
Area
Speed
Number of cycles
Frequency
Power

46. Design tip -- pipeline Delay: 4ns Delay: 4ns
Non-pipelined, critical delay: 8ns
Delay: 4ns
clk
Pipelined, critical delay: 4ns
Delay: 4ns
clk

47. Design tip -- parallel a b c a1 b1 c1 a2 b2 c2
Non-parallel100 data, 100 cycles a b c
Parallel 100 data, 50 cycles a1 b1 c1 a2 b2 c2

48. Design tip -- hardware reuse
state
in1
in2
STATE1 1
n_num
in3
in4

49. Design tip -- hardware reuse1
in1
in3
in2
in4
state
STATE1
n_num

50. Design tip – input buffer
Input Delay
4ns
Delay: 4ns
clk
Input Delay
4ns
Delay: 4ns
clk
clk

51. Design tip – input buffer
No input buffer
Input buffer

52. Example of Design (1/3) A count down counter.
The circuit has three input port: clk, rst, and down.
The circuit has one output port: num.
The circuit is synchronous to posedge clk
The circuit has asynchronous active high reset
If down=1, the circuit begin count from 10 to 0.
If the counter count to 0, it will stay at zero 2 clock cycle and back to 10.

53. Example of Design (2/3)
Step 1: plot the state diagram to describe the circuit behavior.
Step 2: Estimate the essential sequential element.
Step 3: Construct the FSM for control signals based on state diagram.
Step 4: Construct the combinational circuit based on control signals
IDLE
DOWN
ZERO
down =1
count=0

54. Example of Design (3/3) IDLE DOWN ZERO Next state logic count=0
Output logic

55. Editors