1. CPE 626 Advanced VLSI Design, Spring 2002 Admin
Department of Electrical and Computer Engineering University of Alabama in Huntsville

2. ECE-UAH: Adv. VLSI Systems
Outline
Course Info
Course Description
Tentative Syllabus
Grading Policy
Class Policies
Preliminary Essay Info
Preliminary Project Info
Tentative Schedule of Important Class Dates
07/11/2019
ECE-UAH: Adv. VLSI Systems

3. ECE-UAH: Adv. VLSI Systems
Course Info
Instructor
Dr. Aleksandar Milenkovic Office: 217-L Phone: (256) Office Hours: TR 5:30-6:30 PM, or by appointment
Time and Place
Lectures: TR 7:05–8:25 PM, EB 239
07/11/2019
ECE-UAH: Adv. VLSI Systems

4. ECE-UAH: Adv. VLSI Systems
Course Info (cont’d)
Course Web Page
Reference Texts
Peter J. Ashenden,  The Designer's Guide to VHDL (2nd edition),  Morgan-Kaufmann Publishers, 2002 (ISBN: ).
Steve Furber,  ARM System-on-chip Architecture (2nd edition),  Addison-Wesley, 2000 (ISBN: ).
07/11/2019
ECE-UAH: Adv. VLSI Systems

5. ECE-UAH: Adv. VLSI Systems
Course Info (cont’d)
Reference Texts
K. C. Chang,  Digital Systems Design with VHDL and Synthesis - An Integrated Approach,  IEEE Computer Society, 1999.
J. L. Hennessy and D. A. Patterson,  Computer Architecture: A Quantitative Approach, 2nd Ed, Morgan Kaufmann Publishing Co., ISBN:  
Mark Gordon Arnold, Verilog Digital Computer Design: Algorithms to Hardware, Prentice Hall, ISBN
Prerequisites
CPE/EE 427
07/11/2019
ECE-UAH: Adv. VLSI Systems

6. ECE-UAH: Adv. VLSI Systems
Course Description
In the future we will need more customized, application-specific integrated processors which can provide the performance needed at a lower cost than general-purpose architectures. Because cost and time-to-market constraints are very important to such systems, an architecture should permit automatic design, including high-level architectural design. In this course we will present a new design methodology based on using modern hardware description languages such as Verilog/VHDL. The course addresses algorithm, architecture, and implementation aspects of arithmetic processing elements such as adders, multipliers, and dividers, architecture designs of a modern RISC, and floating-point arithmetic processors,design of systems-on-a-chip, and techniques for microprocessor verification. 
07/11/2019
ECE-UAH: Adv. VLSI Systems

7. ECE-UAH: Adv. VLSI Systems
Tentative Syllabus
Week
Topic
1-4
ARM System-on-chip Architecture
5-7
Design Methodology Using HDLs (Verilog) 8
Midterm
9-12
Implementation Aspects: Adders, ALUs, Multipliers, Dividers, Register Files, Buses, CISC/RISC, Memory hierarchy (caches, MMU, main memory)
13-14
Future Directions: Selected Topics 15
Class Presentations
07/11/2019
ECE-UAH: Adv. VLSI Systems

8. ECE-UAH: Adv. VLSI Systems
Grading Policy
Homeworks
20%
Midterm Exam
25%
Essay
10%
Final Exam
40%
Discretion 5%
Grades will be determined on a straight scale.
On occasion I may use a slightly lower scale, but I will never raise the requirements.
07/11/2019
ECE-UAH: Adv. VLSI Systems

9. ECE-UAH: Adv. VLSI Systems
Class Policies
Homeworks must be submitted at the beginning of class on the day they are due. Homework submitted more than one week late will not be graded. Late homeworks will be penalized 30% for the first day late, and 10% per day thereafter. No make-up exam will be given unless you make arrangements with me at least 24 hours in advance. If I do have to create a make-up exam, it will be much harder than the original.
All requests for a re-grade must be submitted in writing within a week of the assignment being returned. No assignment will be re-graded after one week. Please let me know immediately if I have added up your score incorrectly.
07/11/2019
ECE-UAH: Adv. VLSI Systems

10. ECE-UAH: Adv. VLSI Systems
Class Policies
Academic Honesty: Discussing the homework assignments with other students is encouraged, as that is one of the best ways to learn the material. But the work submitted should be your own. All students will be trusted to pursue their academic careers with honesty and integrity. Academic dishonesty includes, but not limited to, cheating on a test or other course work, plagiarism, unauthorized collaboration with other persons. Students found guilty of dishonesty will be subject to penalties that may include suspension from the university.
07/11/2019
ECE-UAH: Adv. VLSI Systems

11. Preliminary Essay Information
Each student should write a survey paper (5-8 pages long) related to advanced VLSI and processor design. The topic should be discussed with the instructor.
07/11/2019
ECE-UAH: Adv. VLSI Systems

12. Preliminary Project Information
The projects will be done in groups of 2 students. Project topics are the choice of each team with the approval of the instructor.
Typical example: develop an HDL description (behavioral and and then RTL - ready for synthesis) for ARM processor core + set of benchmarks used for evaluation
Tools
Mentor Graphics tools are available in Lab 246
You can use other tools (Xilinx Foundation 2.1i, FTL Systems, ...)
07/11/2019
ECE-UAH: Adv. VLSI Systems

13. Preliminary Project Information (cont’d)
Each team will be required to give a minute oral presentation on their design. Each team will also be required to submit a final written report. The format of the report should have form of a ready-for-submission conference paper + all sources, benchmarks, simulation results, etc.
Source code should be well-documented – other people may read or update your source.
07/11/2019
ECE-UAH: Adv. VLSI Systems

14. Tentative Schedule of Important Class Dates
February 07    Project proposals due
February Project assigned
February 28    Midterm Exam
March 21 Essay due
April 18, 23    Class presentations
April 23          Project due  
I reserve the right to change the above schedule based upon the needs of the course.
07/11/2019
ECE-UAH: Adv. VLSI Systems