1. Application of Inline Defect Part Average Testing (I-PAT™) to Identify Potential Latent Reliability Defect Escapes: Feasibility Study Results at NXP
Contributing Authors:
Onder Anilturk, Joyce Witowski, Nikolas Sumikawa, Mommay Ng, et al, NXP Semiconductors N.V.
John C. Robinson, Mike von den Hoff, David Price, Jay Rathert, et al, KLA Corporation
Dan Sebban, Stas Shavlev, Randall Smith, William Usry, et al, Optimal Plus Corporation

2. Agenda Problem Statement & Proposed Solution NXP Feasibility Study
Conclusions

3. Company Overview Total Quality Vision
When our customers think of NXP, we want them to think Total Quality
First time right development, designs and qualification
Deliver zero defects to our customers
Provide flawless customer support
Total Quality is our foundation enabling a Smart, Safe and Secure World
Total Quality Vision
enabled by Quality Mindset & Culture

4. Company Overview Lifecycle analytics for reliable electronics
Accelerating Reliability for Automotive ICs
Lifecycle analytics for reliable electronics
Actionable analytics solutions for smart manufacturing
Serving the leading brands in the automotive, semiconductor and electronics supply chains
Worldwide leader in Quality and Reliability solutions for:
Semiconductor Manufacturing
Packaging
PCB and Flat Panel

5. The Business Problem Increasing semiconductor content per vehicle
$600
Increasing semiconductor content per vehicle
Higher expectations from customers
Tightening requirements
DPPM
<.1 DPPM
Source: Gartner
DPPM – Defective Parts Per Million

6. The Technical Problem: Reliability Defects
Latent reliability defects (LRDs) which become activated after test
Typically partial bridges / opens
Statistically more prevalent in highly defective die
Killer defects in test coverage gaps
No Impact
Defect
Potential Early Life Failure Defect
Look here first
Likely Yield Failure Defect
Fab reliability defects tend to fall into two categories. Both are basically the same The number one fab problem plaguing automotive electronics are a class of defects called “Latent Reliability Defects”.
These are defects that become “activated” some time in the field by repeated use, stress, temperature, etc.
In other words, they do not kill the die at test. They are latent. Some time after test they cause the failure.
Auto suppliers try to reduce this by using various degrees of burn-in– but this is very expensive, impossible to fully simulate all the, and imparts its own reliability concerns) can not tease out all of these problems.
In general, the defect types which lead to reliability failures are generally the same basic defect types that cause yield loss– they are distinguished primarily by size and where they land relative to the device structure.
The simplest manifestation of random defectivity is a particle. A large particle could lands on a line and block a subsequent patterning operation leading to an electrical open.-- in which case the chip will not pass final test and it won’t find it’s way into a car.
But this smaller particle may only partially block the line. It may very well pass final test, but after subsequent cycling in a harsh environment this partial open eventually becomes fully-open. We refer to these defects as latent reliability defects– latent because they are only activated at some time after final test.
Similar mechanisms are at work for shorting defects.
Statistically more prevalent in highly defective die
Partial bridges
Partial opens
Other: resistive contacts…TBD

7. Challenge of Existing Methods
Reliability Defect Escapes
Customer
Field Activation and Failure      
E-Test
Electrical wafer sort
Burn-in
Final Test
Board
Part
Fab
Fab: Sub-samples a small percentage of product to control the process and stop excursions
Electrical Test: Go/No-Go decision ambiguity
Latent defects aren’t easily detectable at test.
Untestable areas 
Coverage versus time-based costs.
 PAT: Parametric outlier analysis helps tremendously, but escapes might still happen.
Zero Defect: How to improve when you’re already doing each individual part extremely well?

8. Breaking Down Silos: Holistic View
Can we do more with the data we already have?
Front-end (FAB)
Process
Limited data sharing between silos
Defectivity & Metrology
Electrical Wafer Sort
Final Test +
FAB
TEST
PCBs,
Systems
Back-end (Test)
Process yield
Time-to-Mkt
Quality
Reliability
Soft Bin, Parametrics
Soft Bin, Parametrics
Most production analytics (outlier detection algorithms) use only electrical wafer sort data

9. Example: Merging Inline Defect Data with Electrical Wafer Sort (EWS) provides clues for potential reliability failures
Which die are most likely to fail?

10. Inline Part Average Testing (I-PAT)
I-PAT is a method for die-level screening based on inline defect results which uses advanced correlation engines to weight defectivity, create a die-level defectivity score, and identify high reliability risk die using statistical outlier detection.
Inspection Layer 1
Stacked map
Inspection Layer 2
Inspection Layer 3
Inspection Layer 4 .
Stack inspection data on reliability relevant layers
Enhance defect data S/N
I-PAT method screens high-risk die with outlier defectivity
Sum of die’s weighted defects
Attributes: Layer, Size, Location, etc.
Statistical approach. Selectable limits
Validate outlier correlation
Inspection Layer 8
Is there a statistical difference in chip reliability between Chip A and B?

11. Optimal+ Outlier Detection Solution - Typical PAT Rule
The solution allows to screen potentially marginal parts by processing a sequence of PAT algorithms on test data
The PAT rule can be defined (and optimized) either using supervised or unsupervised methodologies
Simulations on historical data are usually performed before the PAT rule is deployed for use in volume production
Typical PAT Rule Example

12. Agenda Problem Statement & Proposed Solution NXP Feasibility Study
Conclusions

13. NXP Feasibility Study Overview
Historic analysis:
Defective die that would be screened out at inspection or subsequent tests are used in this study for correlation purposes
Sample population represents 600 wafers (~250k die)
8 Inline defect inspections per wafer (4 FEOL, 4 BEOL) on high sensitivity broadband inspection system
Electrical Wafer Sort, Final Test and Burn-In data used for correlation
Stacked wafer map
NVM stack etch 1
NVM stack etch 2
Post salicide
Post contact barrier
Post metal 1 CMP
Post metal 2 CMP
Post metal 3 CMP
Post last metal CMP

14. Correlation of Inline Defect Outliers with EWS
Observation: I-PAT defect outlier die bins correlate with EWS fallout die
Note: I-PAT results from blind training using defect attribute only: no EWS feedback used to identify I- PAT outlier die, independent validations.
Implication: I-PAT outlier die that somehow pass EWS should be more closely analyzed (e.g., ink-off, burn-in testing, more e-test programs)
Correlation of Defect-Based Die Outliers (I-PAT) with Electrical Wafer Sort (EWS)
EWS Fallout Rate
I-PAT Distribution
High I-PAT Scoring Die are more likely to fail EWS due to defects
Binning is used by O+ to improve the statistics.
These are just example bins. There are many others.
HB124 “HV erase” stress test targeting latent reliability, known to be correlated to BEOL contact to poly overlay, but for the first time it is demonstrated to correlate also to FEOL transistor defectivity – NXP extremely excited!
I-PAT Die Bins
Less defective die
More defective die

15. Defectivity Index (I-PAT) correlation to EWS
I-PAT was correlated to both Wafer Sort and Final Test yield
Drilldown to soft bin and parametric test level can easily be achieved for higher level of granularity in the correlation between defectivity and electrical test performance
Correlation to EWS Yield
Correlation to specific Soft Bin Fallout
Correlation to Parametric
Test performance
Average
Total die count
EWS yield
% bin
I-PAT bin (ascending)
I-PAT bin (ascending)
I-PAT bin (ascending)

16. Defectivity Index (I-PAT) correlation to EWS
I-PAT can identify individual statistical outlier die, and drill down to root cause
Better screening using both test and defectivity data, e.g.
Applying I-PAT defect outlier recognition
Using G-PAT to detect clusters using combination of test and I-PAT data
Bin Map post standard Outlier Detection
Bin Map post enhanced Outlier Detection
Smart I-PAT Map
Bin Map
HB998  I-PAT Static PAT
HB997  G-PAT outliers
(test and defectivity)
HB99  G-PAT (test only)

17. Case Study: BEOL Defects
Cu defect at backend of line (BEOL) metal layers is a potential source of reliability escapes
I-PAT has the potential for early identification of Cu defects, closer to the root cause, and the opportunity to optimize test and enhance screening methodologies.
Cross sectional representation
of Cu void defect
Top Down Cu Defect Examples on die which failed EWS & FT
Fuse

18. Correlation of Inline Defect Outliers with Burn-In
Correlation of Defect-Based Results (I-PAT) with Post-Burn-in Electrical Test
Observation: I-PAT defect outlier die bins correlate with Burn-in fallout die.
Implication: I-PAT outlier die should be more closely analyzed (e.g., P-PAT, G-PAT, etc.).
I-PAT plus additional manufacturing and test are needed to improve prediction  lower false positive (escapes) and lower false negative (unnecessary yield loss)
Burn-in Fallout Rate
High I-PAT Scoring Die are more likely to fail burn-in due to activated latent defects
Burn-In Cumulative Failure Map
Binning is used by O+ to improve the statistics.
These are just example bins. There are many others.
HB124 “HV erase” stress test targeting latent reliability, known to be correlated to BEOL contact to poly overlay, but for the first time it is demonstrated to correlate also to FEOL transistor defectivity – NXP extremely excited!
I-PAT Die Bins
Less defective die
More defective die

19. Burn-In Prediction using Reliability Index (RI)
Burn-In was added in Manufacturing flow as an additional stress test
The motivation is to reduce the cost of Burn-In without impacting Product Reliability
Using Reliability Index, we can define the parts which are more likely to fail during Burn-In and adapt the burn-in testing accordingly per each unit.
Current flow
Defectivity / Metrology
Test
Burn-in
Ship to customer
Pass
Pass
Proposed flow
Input data
Response data
Defectivity / Metrology
Test
ML model for RI
Burn-in
Ship to customer
Pass
Pass
Pass
Skip

20. I-PAT Model Prediction
“Ground Truth” Indicators for Reliability Failure:
SEM Defect Images of known failure modes
Electrical Wafer Sort
Final Test
Burn-in
Field returns
Hit-back analysis
Defect
Weighting
Die-Level Reliability Metric
Correlation Engine
Die Aggregator
Statistical Filter
Inspection Defect Attributes
# of Defects per die
Defect type (rough bin)
Defect size, shape, polarity, etc.
Proximity to critical area
In Die Region (e.g., test coverage gaps)
Defect source analysis
Modeled yield impact
Spatial Signature Analysis
Stacked layers & stacked die position

21. Burn-In failures Prediction – Machine Learning (ML) Flow
I-PAT
Feature reduction
(Big data Analytics)
Supervised multivariate
feature selection
ML modeling
Model validation
EWS
xxx features
xxxx features
xxx features
xx features
Model
Engineering
xxx features
Thousands of features are used to build a Machine Learning model.
The effectiveness of the model depends on the quality of the data and the domain knowledge
Note that this is supervised Machine Learning, i.e. historical burn-in data performance is used to create and validate the model.

22. Engineering Features for ML Model
In addition to existing model input parameters (or features) domain expertise can be applied to increase the amount of features and improve the predictive capabilities of the model
Parametric / Test Engineering Features
Wafer and lot level statistics
Multivariate parameters (such as principal components)
Geographical data such as radius and wafer zones …
Defectivity Engineering Features
I-PAT Model (FE, BE)
Additional defectivity data (such as defect attributes, wafer zones, in-die regions)
Z-axis I-PAT aggregation

23. Next Steps: Adaptive Burn-in*
ML model shows opportunity of reducing Burn-in by 20% with 0 impact to DPPM
This allows to define the threshold for the Manufacturing Reliability-Index
RI threshold
Reliability index
*non-NXP example illustration

24. Next steps: Drilldown to Important Features*
Despite the model not being fully ‘transparent’, it is possible to understand what the most important features are which predict the burn-in outcome
In this example, the top 30 predictive features cover ~ 95% of overall predictive power of the ML model
*non-NXP example illustration

25. Potential Implementation Use Cases
Use I-PAT data to enhance standard Outlier Detection (PAT) rule, that is today based solely on test data
Build and implement ML model based on defectivity (I-PAT) and test data to predict burn-in failures
Feedback information to continuously improve in-line defectivity inspection recipes, and outlier detection rules

26. Agenda Problem Statement & Proposed Solution NXP Feasibility study
Conclusions

27. Conclusions
NXP is striving to raise the bar to identify and eliminate ppb (parts per billion) levels of failure and is continually looking for opportunities to drive quality and achieve zero defects. Participation in this feasibility study is one example of that commitment to quality.
I-PAT has the potential to bring additional data to identify and screen out outlier die containing possible latent reliability defects.
Combination of I-PAT, test data and advanced analytics can be used to identify potential latent reliability defects while reducing overkill and burn-in costs
Continuous improvement (defects classification, I-PAT algorithm, ML model …) is needed to lower cost of screening, and improve product outgoing reliability performance
Future studies include investigation into feasibility of a production implementation of I-PAT

28. Thank you