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Transparent Control Independence (TCI)

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1 Transparent Control Independence (TCI)
Ahmed S. Al-Zawawi Vimal K. Reddy Eric Rotenberg Haitham H. Akkary* *Dept. of Electrical & Computer Engineering *North Carolina State University, Raleigh, NC *Digital Enterprise Group *Intel Corporation, Hillsboro, OR

2 Effect of branch mispredictions
Branch misprediction rate of 5%-10% still a problem Each misprediction squash’s 100s of inst. Reduces performance: limits window size Increases power: useless speculative work © 2007 Ahmed S. Al-Zawawi ISCA 34

3 Control independence basics
© 2007 Ahmed S. Al-Zawawi ISCA 34

4 Control independence basics
© 2007 Ahmed S. Al-Zawawi ISCA 34

5 Control independence basics
© 2007 Ahmed S. Al-Zawawi ISCA 34

6 Control independence basics
© 2007 Ahmed S. Al-Zawawi ISCA 34

7 Four steps for exploiting CI
© 2007 Ahmed S. Al-Zawawi ISCA 34

8 Four steps for exploiting CI
Identify reconv. point © 2007 Ahmed S. Al-Zawawi ISCA 34

9 Four steps for exploiting CI
Identify reconv. point Remove/Insert CD inst. © 2007 Ahmed S. Al-Zawawi ISCA 34

10 Four steps for exploiting CI
Identify reconv. point Remove/Insert CD inst. Identify CIDD inst. © 2007 Ahmed S. Al-Zawawi ISCA 34

11 Four steps for exploiting CI
Identify reconv. point Remove/Insert CD inst. Identify CIDD inst. Repair CIDD inst. Fix data dependencies Re-execute CIDD inst. © 2007 Ahmed S. Al-Zawawi ISCA 34

12 Conventional Recovery vs. Selective Recovery
Squash all instructions after mispredicted branch Rollback state to point of branch Selective recovery (exploiting control independence) Squash only the incorrect CD instructions Don’t rollback future state, repair it

13 Past CI architectures vs. TCI
Repair the future state by repairing in-flight instructions within pipeline structures Explicitly insert/remove CD instructions in ROB, IQ, Phys. RF, etc. Explicitly repair CIDD instructions in the IQ Repair stale source names of CIDD instructions Re-execute CIDD instructions TCI Repair the future state by injecting self-sufficient “recovery program” Recovery is “transparent” to the pipeline

14 TCI microarchitecture
Flash bulb new components Add repair rename map Add selective re-execution buffer (RXB) © 2007 Ahmed S. Al-Zawawi ISCA 34

15 Instructions execute and leave
Predict the branch Instructions execute and leave the pipeline when done © 2007 Ahmed S. Al-Zawawi ISCA 34

16 Construct recovery program
Change red Copy duplicate of CIDD inst. with their source values into RXB © 2007 Ahmed S. Al-Zawawi ISCA 34

17 Insert correct CD instructions
Load branch checkpoint into repair rename map, then fetch correct CD inst. © 2007 Ahmed S. Al-Zawawi ISCA 34

18 Repair & re-execute CIDD instructions
Change red to something bright blue Fix moving Inject duplicate CIDD inst. with their checkpointed source values © 2007 Ahmed S. Al-Zawawi ISCA 34

19 Merge repair & spec. rename maps
Copy corrected register mappings from repair map to spec. map © 2007 Ahmed S. Al-Zawawi ISCA 34

20 High-level view of TCI

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