1. Microprocessors and computers
Architecture and operation
by Mark Horvath
using all the stuff in books and the internet
too much to list here 
last modified:

2. I.1. What is a computer? It’s not trivial!
There are many different types of computers, with different structure, operation and aim.
personal computers, supercomputers, embedded systems, microcontrollers..
Analogue vs digital, binary vs decimal vs trinary, boole – fuzzy - neural – quantum – dna ...

3. Is it one?

4. Or this?

5. Maybe this?

6. What about it?

7. E?

8. And then what is this?

9. Huh?
De! programozható!

10. I.2. Basic principles
Algorithm:
process, method, sequence of steps used to solve a problem
-» program (software)
Interesting fact: „algorithm” comes from the name of Muhammad ibn Musa al-Khwarizmi (cc ), Persian scientist. The word „algebra” comes from the title of his work: „Al-kitāb al-mukhtaṣar fī ḥisāb al-ğabr wa’l-muqābala ”.
The Compendious Book on Calculation by Completion and Balancing

11. Basic principles
Universal, programmable computer

12. Computer (1949)
NASA 1949

13. Computer Computer: originally the people performing the calculations 
Calculator: can do arithmetic operations
Computer: can do arithmetic and logic operations, can be programmed, has a memory
the difference is not obvious

14. Analog computer Can be electronic, mechanical, optical, etc.
Principle of electronic analog computer:
The differential/integral (etc) equations that describe physical processes can be realized in an analogue way with electronic circuits (usually R,L,C and opamps).
Input and output: eg. voltage waveform V(t)
Storing and loading these can be problematic.
Output indication: eg. scope, plotter, deprez
The circuitry can be combined electro-mechanical-optical; similarly the output indication as well (eg. bombsights)

15. Analog computer
Analog computers were often purpose-made and as such, not re-programmable.
Ones made for research and education could be programmed by wiring – practically connecting together mathematical blocks (eg. summing, subtracting, integrating, differentiating amplifiers).

16. Analog computer Advantages:
Theoretically continous range and domain, no quantization noise, but as for all analogue systems, other types of noise are a big problem.
They were much faster (and smaller) for many problems (usu.involving diff.equation systems) in the middle 20th century.
Made obsolete by the ies.
Modern research (little) involves VLSI analog-digital hibrid ICs.

17. Analog computers Top left: slide rule
Bottom left: Norden Mk.XV bombsight
Top right: Akat-1 Polish educational computer
Bottom right: X-15 experimental airplane simulator

18. Digital computer
Input data series is discrete in time domain (sampled) and also in range (quantized).
These are easy to store and reload.
Quantization makes for less precision theoretically, but makes it much more tolerant of noise.

19. Digital computer
A new branch of mathematics was needed to be developed – numerical calculations. It was not trivial how to solve complex diff.equations on quantized and sampled values and what will be the errors.
Programs are easy to store and reload as well. Methods, algorithms need not be re-invented once created.
Digital computers are more versatile. Analog computers were made for a smaller set of problems (imagine reprogramming the same computer from a power plant simulation to mp3 coding).

20. (Digital) Computer
Program: series of calculations and operations that produce an output from an input (mathematically: realization of an algorithm)
Stored program: the program is stored in advance in the computer’s memory, from where it can retrieve it at its own pace

21. Computer
Stored program makes possible to do complex operations and proper timing
Important parts of programs are conditional statements (branching), jumps or subroutine calls, cycles (loops) – these differentiate a real computer from a calculator that can execute a serial program

22. Personal computer For home and office use
It has interfaces and peripherials made for human interaction (display, keyboard, mouse, sound devices, etc)
available for tasks needing low, medium, medium-high calculation speed
typically for interactive programs

23. Personal computer
Apple II
(1977)

24. Personal computer The original IBM-PC (IBM 5150) 1981
(There were a few personal computers before, but IBM popularized the term "Personal Computer")

25. Personal computer
ZX-80 (1980)
ZX Spectrum (1982)

26. Personal computer
Commodore-64
(1982)

27. Mobil computers
Somewhere between a traditional PC and an embedded system
Mobile phone / smart phone, tablet
No need for further explanation right now 

28. Mobil personal computer

29. Supercomputer
For scientific and engineering calculations needing very large number of calculations
Often controlled through other computers (terminals), no human interfaces needed
Very high calculation speed, large number of processors in parallel architecture
Their software often run for days or months
Typically not interactive programs (no human intervention)

30. Supercomputer
IBM's Blue Gene/P supercomputer at Argonne National Laboratory runs over 250,000 processors using normal data center air conditioning, grouped in 72 racks/cabinets connected by a high-speed optical network[1]

31. Embedded system
A computer built into some device, controlling its operation.
Usually lacks in human interfaces or has unusual ones
Often equipped with IO devices to communicate with other devices
Lower-medium calculation speed
Reliability, ruggedness, low power are often requirements

32. Embedded system

33. Embedded system

34. Embedded system

35. Embedded system with human IO

36. II. Operation of microprocessors and computers

37. II.1. Principles of computers
Turing, 1936 „On computable numbers...”
Neumann, 1945 „First Draft of a Report on the EDVAC”
Turing 1946 Automatic Computing Engine
these papers influenced each other, forming a base for what are known as Neumann principles
stored (flexible) program, binary system, use of integers, fixed point and floating point numbers and two’s complement
basic architecture (processor, memory, buses)
Turing 1950 „Computing machinery and intelligence”

38. Neumann principles (computer)
Binary system, number formats
Storage of program and data
basic schematic
(ALU, CU, IO, memory, I-O peripherials)

39. Structure of a computer
Power supply unit, PSU
Mainboard / motherboard
Central Processing Unit, CPU
Memory (RAM, ROM)
Auxiliary circuits (bus drivers, memory controller, clock generator, etc.)
Input-output (IO) circuits (interfaces)
storage interfaces
external communication interfaces (serial, parallel ports, network)
video and audio interfaces, etc.
Peripherials (connected to the interfaces)
human interfaces (keyboard, display, printer, mouse, speaker,etc.)
storage
security systems

40. II.2. Processors
A computer can contain more than one microprocessor or microcontroller.
There is usually one which has a central function, it runs the main software from operating system to user applications, and controls the rest of the computer. This is called the Central Processing Unit (CPU).
Sometimes the computer has more than one parallel microprocessor that together serve the job of CPU; or CPUs can contain more than one parallel "cores".

41. Why microprocessor? Microprocessor  (Motorola 6800, 1974)
 Absolutely not micro processor
Not micro processor 
(PDP-11, 1970)

42. II.2.1 Structure of processors
Processor’s main components:
ALU: arithmetic and logic unit
CU: control unit with control bus connection
registers: small internal memory for holding temporary data
data bus connection (parallel)
address bus connection (parallel): for addressing memory and IO

44. Example

45. Neumann vs. Harvard architecture
Neumann: program and data stored in same way, in same memory
(eg. PC)
Harvard: program and data stored separately, often in separate format (eg. microcontrollers) (otherwise same principles)
Cache in PC processors often include data cache and instruction cache, realizing kind of Harvard arch.
several modified versions, not trivial

46. Operation of a processor
Needs a clock signal (square wave).
Clock edges dictate steps of execution, input and output.
The reading (fetch), execution and write-back for an instruction can take several clock periods.
The clock frequency is not a trivial indicator of a processor’s calculation capability (speed), because of: previous points; parallel execution; pipeline etc.

47. Operation of a processor
Instruction reading (fetch):
CPU puts value of Program Counter (PC) register onto the address bus
CPU uses control bus (IO/M line or similar), that it wants to access memory (RAM or ROM)
CPU uses control bus (R/W line or similar) that it wants to read from memory
Memory's address decoder circuit creates the enable (EN or CS) signal from the address and IO/M signal for the correct memory chip
The memory chip reads the adress and the read signal. In response it puts out on data bus the piece of data (usually 8bit or n*8bit) at the given location.
If needed, it can send a data ready or similar signal for the CPU to signal the data is safely on the bus.

48. Operation of a processor
cont'd.:
CPU reads (fetches) the data in the data bus into its Instruction Register (IR)
CPU increments its Program Counter (this can happen at any time parallel to the previous steps)
CPU's Control Unit (CU) decodes the instruction.
If needed, the rest of the instruction (eg. memory address, constant parameter) is read from the memory (as before)
CU executes the instruction, using the ALU (Arithmetic and Logic Unit) if needed.
If there is a calculation result from ALU, or it was a copying (moving) instruction, the data is written into an internal register or output onto the data bus (for writing into memory, similar as reading but with Write control line). If instruction involved jumping, the Program Counter is changed to the new address (also pipeline is cleared).

49. Clock cycles System clock period (T) Machine cycle (several T long)
does parts eg. fetch, decode-execute, put data on bus
Instruction cycle (several machine cycle long)

50. Pipeline Method for faster overall execution
Main idea is to split instruction execution into several steps which can be done as in a „conveyor belt”
Overall execution speed is n times (if n steps)
Optimal if there aren’t many jumps and forks in the program (have to refill the pipeline)

51. Pipeline Problems with pipeline:
queue (pipeline) has to be reloaded when jumping (conditional or unconditional)
also; in these cases, the instructions already in the queue have been partly executed and may have modified register values -> hazard
an instruction may need a parameter (register or memory value) that will be modified by the previous instruction which has not yet finished with write-back

52. Pipeline solution ideas: jumping: data collision:
when fetching it, fill the next few lines with nop=no operation
in conditinal jumps, branch prediction
static prediction: predict that next line will be executed instead of jump
dynamic: make statistics
prediction esp. useful with cycles; compiler helps with selecting proper machine code instructions to help cpu predict
data collision:
put a nop between two instructions that use the same data;
a flag bit show the register has been modified and delays the next instruction if needed
internal data transfer between pipeline stages

53. Interrupts Hardware interrupt:
An external (to CPU) device can send a signal (interrupt request, IRQ) to the CPU that it needs to deal with it (eg. key pressed on keyboard, mouse moved, printing job done, etc.)
CPU has a hw. input for this (usu. called INT)
CPU can send a signal back (INTA: interrupt acknowledge)
If CPU accepts interrupt, it will execute a subroutine (small program) the deals with the external device

54. Interrupts Types of hardware int.: level triggered: edge triggered:
checks level at certain time during CPU instruction cycle, may be good against impulse noises
edge triggered:
detects change of voltage; needs inside a latch (buffer); may need debouncing

55. Interrupts Software interrupt possibilities:
exceptions or traps in instruction execution (eg. division by zero)
software calls a subroutine (INT instruction), eg. a call to a BIOS or op.sys. routine (eg. draw a character on screen)

56. Interrupt handling
CPU saves PC (program counter) (after increasing it) into the stack
loads the start address of the needed program (ISR: interrupt service routine)
executes the ISR
return (ret, iret or similar) instruction end the ISR, CPU loads PC back from stack and thus returns to original program

57. Stack LIFO (last in, first out) type of memory
Usually part of RAM is reserved for it; can be fixed size (static) or dynamic
Can be physically separate (eg. in microcontrollers)
If it's full, we get a stack overflow error at the next saving into stack. This typically results in our program exiting or "freezing" (infinite loop).

58. Interrupt handling
CPU usually only saves PC to stack; the subroutine has to save other register values (those that will be modified by the routine) and load it back at end of routine
When doing so, we should first give disable interrupt (di) instruction, save the registers and then – if needed – we can enable interrupt (ei) again; same procedure when reloading them. Thus another interrupt can not corrupt the saving process.

59. Interrupt handling vectored interrupt: software IRQ (2nd type):
eg processor hardware IRQ:
inputs TRAP, RST5.5, RST6.5, RST7.5 make the CPU jump to pre-defined addresses (into vector table)
vector table contains pointers, ie. the real starting addresses of the ISRs. The vector table (in RAM) is filled by software (eg. op.sys.)
software IRQ (2nd type):
the starting address is given in the instruction (eg. int 21h (DOS function call))

60. Interrupt handling non vectored int.: eg. 8085: eg. 8086:
The external device that creates the IRQ puts an instruction on the data bus for the CPU to read. This is usually a call or rst, which call a function with the start address given in the instruction
eg. 8086:
similar to above, but this receives a number on the databus, and multiplies it with a constant to get the interrupt vector address

61. Interrupt handling peripherial interrupt controller:
originally a separate external integrated circuit
its inputs are int signals from external devices, its output goes to CPU int input; also connects to data bus
can be programmed with addresses (or offsets) of int.vectors
can be configured for different priority modes (eg. smallest IRQ number has highest priority in IBM PC types)

62. II.2.3 Instruction set (processor)
Instruction set: the set of instructions a processor knows in "hardware".
Machine code: a program containing instructions from the instruction set, in binary or hexadecimal format. It can generally be natively run by the processor (without the need for other software).

63. Assembly
Assembly: lowest level programming language, processor dependent.
It is made by assigning easy to remember words (mnemonics) to machine code instructions; make easier data and number formatting; make labels and constants available; offer some simple functions.

64. Assembly example (8086) clrscr proc near mov ax,0b800h mov es,ax
mov di,0
mov al,' '
mov ah,07d
loop_clear_12:
mov word ptr es:[di],ax
inc di
cmp di,4000
jle loop_clear_12
ret
endp

65. Compiling
Software originally written in other programming languages (not machine code) have to be converted to machine code. In older times, they did it by hand, using conversion tables. Now we use software called compiler. For very high level languages it can involve several middle steps (ie. middle languages).
Question: in what language and machine are compilers written?

66. Instruction categories (examples)
arithmetical: add, subtract, increment
logical: and, or, xor, complement
bitwise: rotate (shift), swap
data manipulate: move, exchange
control: jump, call, return
conditional: jump on condition
I/O: in, out
stack: push, pop

67. Addressing modes of instructions
Immediate addressing:
instr. includes a constant
eg.: mvi register,data (mvi A,9)
Register addressing:
from one register (inside CPU) to another
eg.: mov register1,register2 (2->1) (mov ax,bx)
Direct addressing:
instr. includes a memory address to load data from
eg.: lda address (pl. lda 0xF000)
Indirect addressing:
register (pointer) stores the memory address to load from
eg.: mov register, M (mov A,HL) (HL is the pointer register pair)
Relative addressing
Instr. contains a relative address (offset) from a pre-defined base address (stored also in some registers)

68. Types of instruction sets
RISC: reduced instruction set computer
CISC: complex instruction set computer
other (eg. OISC: one instruction)
as usual the definitions vary with authors and murky

69. CISC
complex instructions (one machine instruction to do complicated stuff)
support of complex data formats (data types)
instructions have many direct and indirect ways of reaching (addressing) contents of RAM (main attribute of CISC according to some authors)
many instructions? (not necessary!)

70. CISC Pro: can be easier to compile from higher level languages (?)
our program (machine code) can be smaller
our program can be quicker if lots of complicated stuff are needed
for versions with small number of instructions, but many ways of memory access (eg. PIC uC), assembly programming can be easier

71. CISC con: CISC is often realized with microcode
asm programming and debugging can be harder if lots of complicated instructions (think PC)
most of complex instructions are used rarely, but use up hardware space and resources in uP
CISC is often realized with microcode

72. microcode
instruction decoding and execution is two-level inside uP: instructions (as seen by programmers) are decoded into a series of even simpler instructions (microinstructions) – effectively realizing CISC with RISC
not seen from outside (even from assembly)
machine code (asm) can be changed without modifying the hardware; similar processor types can have similar machine code, while microcode is different (portability); can emulate another processor
can make uP development and bugfixing easier

73. RISC smaller number of instructions simpler instructions
load/store architecture: there is a simple read and write from RAM into a register, everything else (instructions) is done on internal registers

74. RISC
pro:
more space left in uP desing for making instructions more efficient, faster; also more space for extra registers and special functions
complex instructions are needed rarely, so doing them from software doesn’t slow the program down too much

75. RISC con: try to make all instructions same length
this helps realizing pipeline and timing calculations
con:
might need a better optimized compiler
machine code of program can be larger
slower if too many complex instructions are needed

76. CISC-RISC difference, definition ??:
a uP/uC can have very few, very simple instructions but with complex memory addressing
could have simple load/store memory addressing, but large complex instruction set (as in higher math, matrices etc)

77. Memory addressing
Direct
Banking
Segmented
Virtual

78. Direct: flat / linear memory model
On an address bus of width n bit, 2n byte memory is accessbile (memory cells are usually 1B=8b (or "octet") in size)
eg.:
8085, 6502: 16bit a.bus: 216B=65536B (64kiB)
8086/8088 (IBM-PC): 20bit: 220B= 1MiB
80386, 486, Pentium: 32bit: 232B=4GiB
Pentium-4: 36b: 236=64GiB
x86-64 series (newer) (physically): 252=4PiB
in software, 64b addresses, though some bits of it are currently not used
Of course x86-64 can't currently access all that RAM, but these are designed to actually support 64bit addresses so that the addressing can be updated in the future without having to redesign much hardware and software

79. Bank switching
One "bank" of memory seen at one time. Size of bank is usually the maximum physically addressable.
external circuit helps select actually used bank
a shared memory area can host the op.sys. for example (these areas all point to same memory chip)
typically used with some older processors (eg. with 16b address bus)

80. Memory segmentation
The physically addressable memory is partitioned into smaller blocks called segments.
Logical addrss: segment:offset
Segment address: base address, ie. where the segment starts
Offset: address of memory cell inside segment, ie. distance from base address
Physical address made up of these two:
phys.addr.=segment addr. x 2x + offset

81. Memory segmentation Example: 8086 CPU: 16b data bus, 20b address bus
1MB physically addressable memory
20bit addresses don't fit into 16b registers
16 x 64KiB szegmens
16 segment addresses, 16b offset
phys.addr.=segment*16+offset
it means that segments can overlap

82. Memory segmentation
Segment (base) addresses are stored in CPU's segment registers.
Actually running software usually has to deal with offset only – it's smaller, fits into one 16b register, fetches and executes faster.
Can realize memory protection: separate programs and subroutines can get separate segments, each accesses only its own. Good for protecting op.sys.

83. Memory segmentation
8086 (and in later x86 versions the real mode) segments and segment registers:
Code Segment (CS): for instructions
Stack Segment (SS): for stack
Data Segment (DS): for other data
Extra Segment (ES): string operations and other user defined stuff
8086 didn't have memory (segment) protection yet, later types have.

84. Memory segmentation Variation:
Each program running gets its own main segment. Inside it, it can have its own code segment, data segment, stack segment, etc.

85. Virtual memory
V.M. shows a continous address range for software. In CPU, the MMU (memory management unit) translates virtual address to physical address. The continous range of v.m. can be made up of distinct parts of physical memory.
Using paging, the virtual range can be larger than physically implemented RAM.
Memory protection can be realized when translating virtual addresses.

86. Paging Part of virtual memory mode.
Memory needed by software is partinioned to blocks called pages.
Contents of pages can be in RAM or in background storage (eg. hard disk) (swap file). The page table keeps info on pages location.
If a program needs a page which is not in RAM, a page fault is generated, which causes the system to look for the page in storage and load it to RAM and give it to the program. As such, page faults are not real errors, except if the page doesn't exist anywhere.
Can be used eg. when physically addressable memory is much larger than what is actually implemented (as is case with many computers in the past thirty years). Also, parallel tasks (programs) can use the whole virtual memory range this way, they won't keep it from each other.

87. Memory protection
Running programs (processes) get their own memory area (segment, page, etc.), they get read-write rights for it, but not for others (eg. not for op.sys. areas).
Modern processors can realize it in hardware level. This is attacked by recently (?) discovered exploits known as "Meltdown" and "Spectre". Can also be realized in software (slower and probably less reliable).

88. Storing multi-byte numbers
word: a number (or piece of data) made up of multiple bytes
generally two types of storage/transmission method:
little endian
LSB (least significant byte) first, it is stored at lowest address
easier hardware for addition (starts with LSB)
big endian
MSB (most significant byte) stored at lowest address

89. Storing multi-byte numbers
Little endian:
Intel-AMD x86, x86-64 series
Big endian:
Motorola descendants
AVR32
IBM System/360, z/Architecture
Internet Protocol (IP, TCP, UDP)
Bi-endian (configurable):
ARM 3-tól, PowerPC, Alpha, MIPS, Itanium etc.
May find this problem in communications (eg. connect PC to a data acquisition device)
image source:

90. II.3.1 Mainboard (motherboard)
Includes:
CPU
RAM (working memory)
ROM (stores eg. BIOS, interface drivers)
controller circuits (chipset)
bus connection for peripherial cards and storage

91. Bus system
Bus : set of lines (tracks,wires) carrying the pieces of data
serial or parallel
parallel: eg. 8bit data width: 8 lines, 8bits arrive at the same time
eg. motherboard data bus, address bus, older printer port (LPT), PATA (IDE) (for hard disk)
serial: one line (or one line per direction), eg. 8bits: 8 clock cycles to transmit info
eg. external peripherials (RS232,USB), SATA (hard disk), I2C, SPI (for certain ICs)
NB: Bus is not an abbreviation! So not „BUS”.

92. Simple bus system (mainboard)

93. Example memory connection
4bit dat bus, 8 bit address bus, total 256B memory
of which 1x64B ROM, 3x64B RAM
top 2 bits of address (A7,A6) selects memory module (address decoding with nand gates)

94. Example: ZX Spectrum (Z80)
7805 voltage.regultor
RF modulator (TV out)
logic gates
16kiB ROM
Z80 CPU
CPU quartz
video modulator
video quartz
keyb.conn.
8x 2kiB RAM
ULA (controller IC)
8 x 4kiB RAM

95. ZX Spectrum

96. IBM-PC (8088) (1981)

97. IBM PC-AT (80286) (1984)

98. 80386
CPU clock frequency became higher than ISA bus, so bus interface chip needed
c.1987

99. Pentium
North bridge – south bridge architecture
1993

100. Intel Hub Architecture (IHA)
Pentium Pro - ...

101. Intel PCH
Core series
2008-

102. SBC (Single Board Computer)
also called industrial motherboard
one (usually small sized) mainboard that contains most things necessary for operation of computer
CPU, RAM, Flash (eg. CF card), integrated interface controllers
needs external power, but often only needs a single voltage and has lower power consumption (vs traditional PC)
usually has a special connector for direct control of digital circuits (similar to digital IO of microcontrollers)
often contains PC/104 bus, which is modified ISA bus for industrial applications (eg. connect to data acquisiton (DAQ) cards, relay cards, etc)
some industrial boards are built upon a backplane, that is the cpu is on a separate card

103. SBC

104. II.3.2 Memory
RAM: random access memory: any cell (byte) can be read or written to; usually volatile
ROM: read only memory (usually factory written), non-volatile, fast
EEPROM, Flash: kind of ROM which can be overwritten by user with special methods (non-volatile storage) – read fast, write slow, limited write cycles

105. Memory
ROM: contains software (also called firmware) needed to start the op.system or peripherial cards. Eg. BIOS.
RAM on motherboard: working area of processor. Loads software from storage to RAM and runs them from there; also stores temporary data.
Video RAM: either part of motherboard RAM or separate RAM on video card; contains contents of display

106. BIOS Basic Input-Output System small program stored in ROM
this is read first by CPU when starting computer (booting)
this starts the operating system from the hard disk (or network drive)
provides some function calls for software (basic hardware access)
since PC-AT it includes a program to change some config settings of PC, stored in a special RAM (with its own battery)

107. IO/M selection Separate address space (port mapped IO)
same address can be IO or M
a control bus line selects IO/M
practically same as if that line was added to address bus, thus twice the mem space,
though often the address space usable for IO is less than for M; eg 16b for M and 8b for IO
this limits expansion

108. IO/M selection Memory mapped IO
part of memory address space is reserved for IO units
more flexible
can be fixed or temporary (selectable)
if total memory space is realized by RAM ICs, some parts of it will not be usable
eg. „PCI hole” on PC
eg. PIC microcontroller: IO functions and settings mapped to RAM (Special Function Registers)
x86: both modes, but usually memory mapped; in 64b mode only the latter

109. DMA – Direct Memory Access
used when Memory and IO devices need to communicate
data normally goes through CPU, with DMA it goes through DMA controller (but CPU halts during this)
the DMA controller does this faster than CPU
it can transfer large blocks
these functions can be integrated into bus controller
de bonyolultabb rendszerben (ld pl cache!) cpu dolgozhat tovább

110. DMA
Problem: the bus (mem and data) can only be used by either CPU or DMA controller
byte mode: CPU gains control of bus between transfers (eg. to read its instructions) (cycle stealing) – eg in real time systems
burst mode : large blocks, CPU is on hold
interleaved: if memory clock faster than cpu, they use bus in alternating mode
transparent: DMA waits for bus being freed
if there is a cache, CPU can go on working during DMA transfer, but this can result in difference btw contents of cache and RAM (cache incoherence) – cache must be written out to RAM before DMA operation

111. DMA ISA bus: there are 1 or 2 DMA controllers, 4 or 8 DMA channels
PCI bus: no central controller; any PCI device can ask the PCI controller (south bridge) to gain control of the bus
...

112. SRAM (Static RAM)
Every bit is a flip-flop. One flip-flop is usually 6 transistor. There is also a 4 transistor + 2 resistor variation (smaller but more power consumption).
Compared to DRAM:
Keeps value as long as it has voltage supply - no need of refreshing.
Faster than DRAM.
Less bits per unit area (data density).
Easier control.
More expensive.
Found mostly in microcontrollers and cache.

113. DRAM (Dynamic RAM) Each bit is a transistor + a capacitor.
large data density
needs periodic refreshing using external or built-in control electronics (capacitor discharges)
RAM is made up of rows and columns; entire row is refreshed at once
for DDRAM with 8192 rows, there is 7.8us refresh cycle resulting in 64ms total refresh time
Used in large memory: mostly PC RAM

114. ECC-RAM
Error correcting code
9b RAM, 9th bit for error correction

115. Cache Method for increasing effective speed
RAM outside of uP is slower
DRAM slower than SRAM (but larger capacity)
cache: small capacity, fast SRAM inside CPU

116. Cache
from external RAM we load into the cache such data that will be needed in the near future
part of the running program
necessary variables, data
contents must be synchronized with RAM
needs complex control circuitry
can be multi-level

117. Cache
AMD Athlon 64

118. Special systems OISC: one instruction set computer
Transport trigger architecture: use mov instruction to write into special registers, instead of simple memory write, each register will execute a different instruction. Eg. -> MAXQ microcontroller
Arithmetic: eg. SBNZ a,b,c,d
c=a-b and if c=0, jump to d

119. II.6. Processor examples

120. 4004

121. 8008 (more detailed)

122. 8080

123. 8085

125. Z80

126. Z80

127. Z80 test circuit

128. 8086

129. 8087 FPU (Floating point unit)