1. Computer Structure PC Structure and Peripherals
Lihu Rappoport and Adi Yoaz

2. Hard Disks

3. Hard Disk Structure Rotating platters coated with a magnetic surface
Each platter is divided to tracks: concentric circles
Each track is divided to sectors
Smallest unit that can be read or written
Outer tracks are longer than inner tracks
Constant bit density: record more sectors on the outer tracks
Transfer rate (bit/sec) varies with track location
Moveable read/write head
Flies close to disk surface
Radial movement to access all tracks
Platter rotation to access all sectors
Buffer Cache
A temporary data storage area used to enhance drive performance
Track
Sector
Platters

4. SATA+Power connection
Hard Disk Structure
SATA interface
SATA 3: 6Gb/s with 8/10 encoding (600 MB/sec effective)
SATA+Power connection
To HDD

5. Disk Access Seek: position the head over the proper track
Average: Sum of the time for all possible seek / total # of possible seeks
Due to locality of disk reference, actual average seek is shorter
Rotational latency: wait for desired sector to rotate under head
The faster the drives spins, the shorter the rotational latency time
Most disks rotate at 5,400 to 15,000 RPM
At 7200 RPM: 8 ms per revolution  4ms on average for ½ revolution
Transfer block: read/write the data
Transfer time is a function of: sector size and rotation speed
Typical values: 200 MB / sec
Transfer speed (bit/sec) depends on rotation speed and recording density (bits per inch on a track)
Disk Access Time = Seek time + Rotational Latency + Transfer time
+ Controller Time + Queuing Delay

6. HDD Spec Example WD Blue 6TB WD Black 6TB Basic specs
Formatted Capacity
6TB
Rotational Speed
5400 RPM
7200 RPM
Buffer Size (cache)
256 MB
Load/unload Cycles*
300,000
Interface (Serial ATA)
600 MB/sec
Max sustained data rate
180 MB/s
227 MB/s
 Acoustics
Idle Mode
23 dBA
29 dBA
Seek (average)
27 dBA
36 dBA
Power
Read/Write
4.8
9.1
 (Watts)
Idle
3.1
7.1
Standby/sleep
0.6
1.0
* Power on/off. Mobile computers turn off HDD to save power frequently

7. Flash Memory and SSD

8. Flash Memory Flash is a non-volatile, rewritable memory
Erasing – setting all the bits, Write/Program - clearing a bit
Writing a value requites an erase operation followed by a write
Information is stored in an array of memory cells
Single-level cell (SLC) devices: each cell stores one bit
Multi-level cell (MLC) devices: each cell stores 2 bits (using 4 voltage levels)
Three-level cell (TLC) devices: each cell stores 3 bits (using 8 voltage levels)
NOR flash
NAND flash
Read/write granularity
Byte
Page (0.5KB – 4KB)
Erasing granularity
Block (64-256KB)
Block (64-512KB)
Usage
Storing code (BIOS, firmware)
Storing large data
Storage capacity
Low
High
Cost per bit
lower

9. Flash Memory Write Endurance
Typical number of write cycles
Bad block management (BBM)
Performed by the device driver software, or by a HW controller
E.g., SD cards include a HW controller perform BBM and wear leveling
Map logical block to physical block
Mapping tables stored in dedicated flash blocks
Each block checked at power-up to create a bad block map in RAM
Each write is verified, and block is remapped in case of write failure
Memory capacity gradually shrinks as more blocks are marked as bad
ECC compensates for bits that spontaneously fail
22 (24) bits of ECC code correct a one bit error in 2048 (4096) data bits
If ECC cannot correct the error during read, it may still detect the error
SLC
MLC
TLC
NAND flash
100K
2K-10K 1K
NOR flash
100K - 1M
10K

10. Flash Write Endurance (cont)
Wear-leveling algorithms
Evenly distribute data across flash memory and move data around
Prevent from one portion to wear out faster than another
The flash controller keeps a record of where data is set down on the drive as it is relocated from one portion to another
Dynamic wear leveling
Map Logical Block Addresses (LBAs) to physical Flash memory addresses
Each time a block of data is written, it is written to a new location
Link the new block
Mark original physical block as invalid data
Blocks that never get written remain in the same location
Static wear leveling
Works similarly to dynamic wear leveling
Also periodically move blocks which are not written
Allow low these usage cells be used by other data

11. Solid State Drive – SSD SSDs use a NAND flash
The more write/erase cycles  the shorter the drive's lifespan
Use wear-leveling algorithms to evenly distribute writes
DRAM cache to buffer data writes to reduce number of write/erase cycles
Extra memory cells to be used when blocks of flash memory wear out
SLC
MLC
TLC
Bits per cell 1 2 3
P/E cycles
100K
2K-10K 1K
Read time
25μs
50μs
75μs
Program time μs μs μs
Erase time
1.5-2 ms
3 ms
4.5 ms
Higher Density / Lower cost
Higher Performance and Endurance

12. SSD (cont.)
Data in NAND flash memory is organized in fixed size blocks
When any portion of the data on the block is changed
Mark block for deletion in preparation for the new data
Read current data on block, and create an image of the new data
Write the new image (either to the current block or to anew block)
Write amplification is the ratio between the block size and the new data
Typical write amplification is 15 to 20
For every 1MB of data written to the drive, 15MB to 20MBs of space is actually re-written
Using write combining reduces write amplification to ~10%
Flash drives compared to HD drives
Smaller size, faster, lighter, noiseless, lower power
Withstanding shocks up to 2000 Gs (like 10 foot drop onto concrete)
More expensive (cost/byte): ~0.3$/1GB vs ~0.03$/1GB in HDD

13. SSD vs HDD Attribute SSD HDD Power 2 – 4 watts 5 – 10 watts Cost
$0.20 per gigabyte (for 1TB drive)
$0.03 per gigabyte, (for 4TB drive)
Max capacity
1TB for notebooks
4TB for desktops
2TB for notebooks
10TB for desktops
OS Boot Time
10-13 seconds
30-40 seconds
Noise/Vibration
Silent, no vibrations
Clicks, spinning, possible vibrations
Failure Rate (MTBF)
2.0 million hours
1.5 million hours
File Copy / Write Speed
200 MB/s MB/s
50 – 120MB/s
Access time
25μs – 50μs
4ms
Shock
2000G
60G (operating) 350G (parked)
Form factor
2.5”, M.2
3.5”, 2.5”, 1.8”

14. The Motherboard

15. Personal Computer System
USB
HDMI
PCH
Platform Controller Hub
DMI×4
FDI
LAN 10/100/1000
SATA
Audio Codec
Line out
Mic
BIOS
PCIe ×16
PCIe ×1,×2,×4 Slots
Graphics
Core
LLC
System Agent
Display
DMI
PCIe
IMC
Display
Port
2ch DDR3
DMI – Direct Media Interface
FDI – Flexible Display Interface

16. Motherboard Layout Micro-ATX (desktop) audio header
PCI express x1 connector
PCI express x16 connector
Back panel connectors
CPU power connector
Processor socket
Processor fan header
DIMM Channel A sockets
Serial port header
DIMM Channel B sockets
Main Power connector
Battery
SATA connectors
Front panel USB2 headers
Bios setup config jumper
High Def. Audio header
S/PDIF
speaker
Front chassis fan header
Chassis intrusion header
Rear chassis fan header
PCH
PCI connector
Reset, power, Front LEDs
Front panel USB3 headers
Micro-ATX
(desktop)

17. Motherboard Back Panel
USB 2.0 ports
LAN port
USB 3.0 ports
eSATA
DisplayPort
HDMI
DVI-I
IEEE
1394A
Rear
Surround
Line in
Line out/
Front speakers
S/PDIF
Center / subwoofer
Mic in / Side
surround

18. USB – Universal Serial Bus
An industry standard for external peripheral connection to a PC, as well as for power supply
Provides specification for cables, connectors and protocols
USB 2
USB 3
Speed
480 Mbit/sec
4.8 Gbit/sec
Power Usage
Up to 500 mA
Up to 900 mA
Number of wires within the cable 4 9
Standard A Connectors
Grey in color
Blue in color
USB3 type A is backward compatible with
USB2 type A

19. USB-C USB-C standard defines new connector and cable
USB-C connector vs. USB3 type A connector:
Supports / May support / Will Support
USB 3.1 gen 1 – 5 Gbit/sec, gen 2 – 10 Gbit/sec
USB 3.2 – up to 20 Gbit/sec
Audio Adapter Accessory Mode - analog headsets
Alternate Modes
DisplayPort digital display interface, supports 8K (7680 × 4320) at 60Hz with 30 bit/px RGB color and HDR (High-dynamic-range video)
HDMI 1.4b – High-Definition Multimedia Interface supports 4K (3840 × 2160) at 30Hz digital video with 30 bit/px RGB color, and 8 channel LPCM/192 kHz/24-bit digital audio
Thunderbolt 3 – external peripheral connection, supports up to 40 Gbit/sec, combines PCIe and DisplayPort into two serial signals, uses USB-C connector
And more

20. PCI Express (PCIe)
Replaces the older PCI (Peripheral Component Interconnect) bus
high-speed serial computer expansion bus standard, used for attaching hardware devices (add-on cards)
GFX cards, network cards, sound cards, modems, disk controllers, etc
Devices are assigned addresses in the processor's address space (MMIO)
PCI Express Layered Protocol
Compatible with the PCI addressing model
All existing applications and drivers operate unchanged
SW layers generate read and write requests
HW layers
Transaction layer: splits data to packets
Data Link Layer: ensures data integrity: adds sequence numbers and CRC per packet
The Physical Layer – transmit the packets SW HW
Physical Layer
Data Link Layer
Transaction Layer
PCIe Device Driver
PCI Plug-n-Play
Operating System

21. PCI Express Physical Layer
Transport packets between the link layers of two PCIe agents
The fundamental PCI Express link
Serial communication
Point to point transmit pair and receive pair
2.5G transfers/sec/direction provide 200MB/s
PCI Express link bandwidth may be linearly scaled
By adding signal pairs to form multiple lanes
The physical layer supports x1, x2, x4, x8, x12, x16 and x32 lane widths
A PCI Express card fits into a slot of its physical size or larger
During initialization
Each PCIe link is set up following a negotiation of lane widths and frequency of operation by the two agents at each end of the link
No firmware or operating system software is involved

22. PCI Express Link Layer
Ensure reliable delivery of packets across PCI Express link
Responsible for data integrity
Adds a sequence number and a CRC to the transaction layer packet
A credit-based, flow control protocol
Ensures that packets are only transmitted when it is known that a buffer is available to receive this packet at the other end
Eliminates packet retries  saves waste of bus bandwidth
Automatically retry a packet that is signaled as corrupted

23. PCI Express Transaction Layer
Receives read and write requests from the SW layer
Creates request packets for transmission to the link layer
Some of the request packets need a response packet
Receives response packets from the link layer
Matches them with the original SW requests according to unique identifier
Packet format supports 32bit and extended 64bit memory addressing
Packets have attributes (e.g., “no-snoop”, “relaxed-ordering”, “priority”)
Used to optimally route these packets through the I/O subsystem
Supports four address spaces
The three PCI address spaces: memory, I/O, and configuration
A Message Space: can be thought of as “virtual wires”
Eliminates hard-wired sideband signals used in PCI
Interrupts, power-management requests, resets
Uses Message Signaled Interrupt (MSI) to propagate system interrupts

24. System Start-up Upon computer turn-on several events occur:
1. The CPU "wakes up" and sends a message to activate the BIOS
2. BIOS runs Power-On Self-Test (POST): make sure system devices are working ok
Initialize system hardware and chipset registers
Initialize power management
Test RAM
Enable the keyboard
Test serial and parallel ports
Initialize disk drive controllers
Displays system summary information

25. System Start-up (cont.)
3. During POST, the BIOS compares the system configuration data obtained from POST with the system information stored on a memory chip located on the MB
A CMOS chip, which is updated whenever new system components are added
Contains the latest information about system components
4. After the POST tasks are completed
The BIOS looks for the boot program responsible for loading the OS
According to a pre-defined order of devices (DVD, USB stick, HDD)
5. After boot program is loaded into memory
It loads the system configuration information contained in the registry in a Windows® environment, and device drivers
6. Finally, the operating system is loaded