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Minimum Complexity Non-blocking Switching

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Presentation on theme: "Minimum Complexity Non-blocking Switching"— Presentation transcript:

1 Minimum Complexity Non-blocking Switching
Mario Baldi Politecnico di Torino staff.polito.it/mario.baldi Yoram Ofek Università di Trento Achille Pattavina Politecnico di Milano

2 Time-Driven Switching
Low routing complexity No-header processing Low buffer requirement Low switching complexity Architecture and control Aligned switching Pre-computed switching fabric configuration Fabric Banyan

3 A Potential Problem Scheduling resulting in blocking

4 As connections/flows are set up
time frames are reserved on each link. Reservation vectors Scheduling time cycle As more connections/flows are setup …

5 … more time frames are reserved
Since nodes forward packets during the time frame following their reception … … the time frames on a link follow the ones on the upstream link. … more time frames are reserved As more connections/flows are setup on different paths…

6 … the reservation vectors grow fuller.

7 … multiple possible schedules may exist.
Still, when setting up a new connection/flow...

8 … even though enough capacity is available on all the links.
However, scheduling may be impossible. Not possible Not possible Blocking Not possible

9 Simulation Results 1000 TFs 64 TFs 32 TFs 16 TFs 1 TF

10 Turning the Potential Problem into a Major Advantage
Banyan switching fabric N a { Minimum complexity: a•N •lgaN

11 Blocking 1 1 2 2 3 3 4 4 But only within the same time frame

12 Conflicts are minimized
The Intuition Conflicts are minimized across multiple time frames

13 Simulation Results

14 Lia’s Theorem v v: number of vertical replications that ensure the switch to be non-blocking

15 Time-space equivalence
Selecting one out of k TFs in a time-driven switch is equivalent to selecting one out of k vertically replicated switching fabrics A time-driven switch with a single Banyan fabric is non-blocking up to a load (k-v)/k

16 Ongoing Work Formal Proof Simulation Network of switches
Basic time-space equivalence theorem Effect of speed-up Simulation Validation of analysis Behavior at higher loads Network of switches Analysis


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