1. how they work and how Python helps designing one
Ternary CPUs:
how they work and how Python helps designing one
Cesare Di Mauro
PyCon X – Florence
May 2019
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

2. Computers use a binary numeral system (two symbols)
In the beginning it was… binary!
Computers use a binary numeral system (two symbols)
Two symbols that may represent:
0, 1
False, True
Off, On
-, +
Numbers:
1·26 + 1·25 + 0·24 + 0·23 + 1·22 + 0·21 + 0·20
10010
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

3. Commonly defined conventions
Information in base-2
Commonly defined conventions
Bit: one binary digit
0 or 1, False or True, etc.
3 bits: one octal digit
0002 = 08 = 010, …, 1112 = 78 = 010
4 bits: one nibble  one hex (hexadecimal) digit
00002 = 016 = 010, …, = F8 = 1510
8 bits: one byte
= 010, …, = 25510
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

4. Integers in base-2 Signed numbers: two’s complement
10010 = =
8 bits: one byte
unsigned: signed:
16 bits: two bytes
unsigned: signed:
32 bits: four bytes
unsigned:
signed:
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

5. A ternary numeral system uses three symbols
Now it’s ternary time!
A ternary numeral system uses three symbols
Three symbols may represent:
0, 1, 2
-1, 0, 1
-, 0, +
False, True, Unknown
Numbers:
1·34 + 0·33 + 2·32 + 0·31 + 1·30
10010
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

6. Encoding information in base-3
Three symbols = one ternary digit = one trit
0 or 1 or 2, -1 or 0 or 1, - or 0 or +, etc.
Three symbols ≠ +50% over two symbols (base-2)!
Encoded information = log 3 log 2 = … bits
Example:
two trits = 32 = 9 symbols vs three bits = 23 = 8 symbols
Two trits ≠ three bits: we have one more symbol available!
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

7. Signed numbers in base-3*
Decimal  
Biased  
2’s Comp. 
3’s Comp.   
Bal. Ter. 4
    22    — 11 ++ 3 21 10 +0 2 20 02 +- 1 12 01 0+ 00 –0 –1 0- –2 -+ –3 -0 –4 --
Trit: one ternary digit
0 or 1 or 2, -1 or 0 or 1, - or 0 or +, etc.
3 trits: one tribble 33 == 27 symbols
Balanced Ternary: -, 0, and + are shortcuts for -1, 0, and +1.
Example: -0+ = (-1)·32 + 0·31 + 1·30 = = -8 *
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

8. Same as base-2: defining conventions
Defining the “Tribble”
Same as base-2: defining conventions
3 trits: one tribble 33 = 27 symbols
0003 = 010, …, 2223 = 2610
From Hexadecimal (base-16) to Heptavintimal (base-27)
ABCDEFGHKMNPRTVXZ*
Heptavintimal “pack” more information when representing ternary numbers/data; similar to hexadecimal vs binary.
Example: 20 trits are represented by 7 tribbles (hept digits). *
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

9. Defining the “Tryte”
Possible choices for the byte equivalent: 5, 6, or 9 trits.
5 trits: -13 symbols*  losing some information
unsigned: signed:
6 trits: +473 symbols*  much more information
unsigned: signed:
9 trits: symbols*  way more information!
unsigned: signed:
My personal choice: 1 tryte = 5 trits. Closely matches a byte.
*Compared to one byte
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

10. Integers in base-3 5 trits: one tryte
unsigned: signed:
Reference: ±10010
10 trits: two trytes
unsigned: signed:
Reference: ±10,00010
20 trits: four trytes
unsigned:
signed:
Reference: ±1,000,000,00010
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

11. Floating points in base-3
fp20
1 tryte for exponent  (in base-3! Wider range)
3 trytes for mantissa & sign  6-7 decimal digits*
20-trits float in base-3 ≈ 32-bit float in base-2
fp40
7 trits for exponent  (in base-3! Wider range)
33 trits for mantissa & sign  decimal digits*
40-trits float in base-3 ≈ 64-bit float in base-2
*A bit less information is available, due to a slightly small mantissa range, and the sign which is encoded into the mantissa.
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

12. The 3ISA – Ternary Architecture
Like almost all modern ISAs: it’s a N-RISC*
Not-Reduced Instruction Set Architecture (more CISC-like)
Many instructions (and room for more)
Not only “simple” instructions (even multi-cycles ones)
Variable-length opcodes
2 trytes minimum (10 trits. Then 15, 20, 25, etc.)
Base ISA is fixed-length: 4 trytes (20 trits)
Load & store
Feature-complete: “integer” (scalar), FPU, vector/SIMD
* Pag.2 “Design goals for RISC I”
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

13. The 3ISA opcodes structure
Compact opcodes (Integer)
2 trytes (10 trits)
3 trytes (15 trits)
Standard/base opcodes (Integer, FPU)  Implemented
4 trytes (20 trits)
Vector (SIMD with masks. Like Intel’s AVX-512) opcodes
5 trytes (25 trits)
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

14. General specs 27 General purpose registers R0..R26.
R0 fixed to zero (not writable  fault raised).
R1 used as a stack pointer (PUSH/POP instructions).
R26 used as link register (CALL instructions).
GP registers are either 20 or 40 trits (4 or 8 trytes).
1 PC (Program Counter) register (20 or 40 trits).
1 F (Flags) register (20 or 40 trits). User-mode.
Note: the architecture is little-endian (LSTrit/Tryte first).
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

15. Float and vector registers
27 FPU & Vector registers F0..F26 or V0..V26.
Shared (e.g.: F0 = lower part of V0).
10, 20, 40, or 80 trits FPU registers (depending on the supported maximum floating point precision).
Roughly equivalent to fp16, fp32, fp64, fp128 in base-2.
Minimum vector registers size = maximum FPU registers size.
Maximum vector size depends on specific implementation (e.g. ISA is variable-length & length-agnostic).
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

16. Instructions groups Quaternary (3 sources, 1 destination)*
Binary (1 source, 1 destination)*
Unary (1 source or destination)
User mode & privilege mode
Calls (jump & link using R26)
Conditional jumps (up to 27 conditions), cmp regs & jump
Load & Store (one address mode: base reg + offset)
Loads with immediate. Load immediate from PC
*Support quick immediate as the last source
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

17. Ternary (diadic) instructions
Most are common:
Arithmetic  ADD, ADDC, SUB, SUBC
Shift/rotate  SHL, SHR, SAR, ROL, ROR, RCL, RCR
Logical ones are quite different*:
TMIN  Ternary AND, TMAX  Ternary OR
TANTIMIN  Ternary Antimin (NAND)
TANTIMAX  Ternary Antimax (NOR)
TXOR  Ternary XOR
New ones*:
TSUM, TANY, TEQUAL, TCONS *
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

18. Binary (monadic) instructions
Some are common: MOV, CMP, TEST
Logical ones (NOT, specifically) are quite different*:
STI  Standard Ternary Inverter
NTI  Negative Ternary Inverter
PTI  Positive Ternary Inverter
New ones*:
ISUNK  Is Unknown, ISFALSE  Is False, ISTRUE  Is True
SHIFTD  Shift Down, SHIFTU  Shift Up
ROTD  Rotate Down, ROTU  Rotate Up
SWAPN  Swap Negative, SWAPP  Swap Positive *
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

19. The 3ISA assembler specs
Supports:
all 3ISA (integer) instructions
directives (ORG, EQU, SET, PRINT)
labels and local labels (e.g. internal to subroutines)
comments
data constant & storage definition
expressions with classic unary (+, -, ~) and binary (<<, >>, &, !, ^, *, /, %, +, -, =, <, >, <>, <=, >=) operators
decimal, binary, octal, hexadecimal literals
single quoted and double quoted strings
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

20. 3ISA assembly example
L2Next EQU l PRINT L2Next L2Size SET L2 - Label cmpjs r14,r26,L2 loadl loadh r2,$D loadpc r2,% load5 r3,[r4,13] store5 r3,[r4,-81] loadu5 r3,[r4,243] DC.T 'A' L0 DC.T 1, $f, 'A' DS.L 5
Start ORG 12 .LocalLabel: PRINT .LocalLabel PRINT * add r1,r2,r3; Comment mov r1,r2 cmp r1,r call r add r1,r2, mov r1, cmp r1,-4 Label: call l2 call r13,13 L2 jz Label
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

21. ANTLR (ANother Tool for Language Recognition)
Building the assembler: ANTLR
ANTLR (ANother Tool for Language Recognition)
Parser generator for:
lexer
(language) syntax parser
AST (Abstract Syntax Tree)  Tree walker
A single grammar for all parsers!
Parsers generated for several languages (Python included)
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

22. The ANTLR grammar for 3ISA
grammar asm3isa; options { language = Python2; // Generated code for Python. } module // This is the main/start rule. : (line? NEWLINE)+ ; line : directive | compound_instruction | standalone_label | standalone_comment ; standalone_label: label ':’;
comment: ~NEWLINE*; standalone_comment: ('*' | ';') comment; label: SYMBOL {self.define_label($SYMBOL)}; // Embedded Python code.
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

23. ANTLRWorks2: an ANTLR tool
ANTLRWorks2 is an IDE to help develop ANTLR grammars
It can generate syntax diagrams for rules
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

24. The generated object file
The object file: a pure sequence of trits?!?
Representing trits on a binary system:
-  002
0  012
+  102
Space wasted (e.g.: 112 not used):
1 trit  2 bits. 1 tryte  10 bits.
Object file  sequence of bytes
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

25. Testing assembler and emulator
Assembler testing goals:
Check ternary (the expected one)
Check stdout (expected)
Emulator testing goals:
Initialize the emulator state
Check conditions all times (invariants)
Check final state (post-conditions)
Assembler and emulator goals:
Same assembly code for assembler and emulator
More complex test scenarios
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

26. No code: “just” simple, explicit, readable declarations…
Beautiful testing with Python
class TernaryTests(BaseTest): @expected_ternary(' ') @expected_output('') @init(r2=2, r3=3) @postconditions(r2=2, r3=3, exception=WriteToR0) def test_write_to_r0(self): """add r0,r2,r3""" @expected_ternary(' ') @init(r2=2, r3=3) @invariants(r2=2, r3=3) @postconditions(r1=5, r2=2, r3=3, pc=4, f=9) def test_add(self): """add r1,r2,r3"""
No code: “just” simple, explicit, readable declarations…
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

27. Exceptions can be trapped and checked
How the trick works
@init(r2=2, r2=2, r3=3, pc=4, f=9)
Decorators collect all requirements
args or kwargs are stored in test method
Requirements used & checked by “test executor”
@postconditions(r2=2, r3=3, exception=WriteToR0)
Exceptions can be trapped and checked
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

28. Reusing standard Python features
class TernaryTests(BaseTest): def test_add(self): """add r1,r2,r3"""
Doc string  3ISA assembly source code
Doc string is compiled and used (run) by “test executor”
class EmulatorTests(BaseTest): @postconditions() def test_init(self): assert len(self.emulator.memory) == 0, "The emulator memory is not empty!"
Method code  extra, more complex, conditions
Method code is executed by “test executor” after emulator execution and post-condition checks.
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

29. Testing framework limits
Emulator’s memory status not yet testable on invariants and post-conditions checks.
Assembler should be run as separate process (and killed on timeout) to avoid deadlocks (e.g.: compilation never completes).
Same issue for emulator (e.g: never-ending loops).
Invariants checks totally own emulator’s single-step execution. Single-step cannot be used/tested by per-se
Assembler’s stderr not intercepted/collected and checked.
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

30. Conclusion PROs Better code density  20 trits ≈ 32 bits for opcodes
Better data density  5/10/20 trits ≈ 8/16/32 bits for data
Much less wiring (and chip area)*
Better power consumption
CONs
Effort to convert/adapt existing software
New encodings needed (e.g.: ASCII, UTF-8, RGB, etc.)
Interfacing with existing binary world
Possible lower frequencies reached for chips (3 states) *
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

31. Bibliography / references
The Ternary Manifesto
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science
Ternary Computer System Project
By Claudio La Rosa (thanks for involving me!)
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

32. The first ternary computer board
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one

33. Q&A
May 2019
Cesare Di Mauro – PyCon X Ternary CPUs: how they work and how Python helps designing one