Presentation on theme: "Transistors and Logic A B The digital contract"— Presentation transcript:
1 Transistors and Logic A B The digital contract Comp 411Box-o-TricksF = A xor BThe digital contractEncoding bits with voltagesProcessing bits with transistorsGatesTruth-table SOP RealizationsMultiplexer Logic
2 Where Are We? Things we know so far - 1) Computers process information2) Information is measured in bits3) Data can be represented as groups of bits4) Computer instructions are encoded as bits5) Computer instructions are just data6) We, humans, don’t want to deal with bits…So we invent ASSEMBLY Languageeven that is too low-level so we invent COMPILERs, and they are too rigid so …Biological processes next big frontier in information processing. Will course 6 be obselete? No! A lot systems engineering is independent of the base technology.But, what PROCESSES all these bits?
3 A Substrate for Computation We can build devices for processing and representing bits using almost any physical phenomenonWait! Those last onesmight have potential...neutrino fluxtrained elephantsengraved stone tabletsorbits of planetssequences of amino acidspolarization of a photon
4 Using Electromagnetic Phenomena Things like:voltages phasecurrents frequencyFor today let’s discuss using voltages to encode information.Voltage pros:easy generation, detectionvoltage changes can be very fastlots of engineering knowledgeVoltage cons:easily affected by environmentneed wires everywhere
5 Representing Information with Voltage Representation of each point (x, y) on a B&W Picture:0 volts: BLACK1 volt: WHITE0.37 volts: 37% Grayetc.Representation of a picture:Scan points in some prescribed raster order… generate voltagewaveformHow much informationat each point?
6 Information Processing = Computation First, let’s introduce some processing blocks: (say, using a fancy photocopier/scanner/printer)vCopyINVv1-v
7 Let’s build a system!inputCopyINV(In Theory)(Reality)?output
8 Why Did Our System Fail? Why doesn’t reality match theory? 1. COPY Operator doesn’t work right2. INVERSION Operator doesn’t work right3. Theory is imperfect4. Reality is imperfect5. Our system architecture stinksANSWER: all of the above!Noise and inaccuracy are inevitable; we can’t reliably reproduce infinite information-- we must design our system to tolerate some amount of error if it is to process information reliably.
9 The Key to System Design A SYSTEM is a structure that is guaranteed to exhibit a specified behavior, assuming all of its components obey their specified behaviors.How is this achieved?ContractsEvery system component will have clear obligations and responsibilities. If these are maintained we have every right to expect the system to behave as planned. If contracts are violated all bets are off.
10 The Digital Panacea ... Why DIGITAL? … because it keeps the contracts SIMPLE!The price we pay for this robustness?All the information that we transfer between components is only 1 crummy bit! But, in exchange, we get a guarantee of a reliable system.0 or 1
11 The Digital Abstraction “Ideal” Abstract WorldReal World0/1Manufacturing VariationsBitsNoiseVolts orElectrons orErgs or GallonsKeep in mind, the world is not digital, we engineer it to behave that way. We must use real physical phenomena to implement digital designs!
12 A Digital Processing Element A combinational device is a circuit element that hasone or more digital inputsone or more digital outputsa functional specification that details the value of each output for every possible combination of valid input values output depends only on the latest inputsa timing specification consisting (at minimum) of an upper bound tpd on the time the device will take to produce the output value from stable valid input valuesStaticDisciplineOutput a “1” if atleast 2 out of 3 ofmy inputs are a “1”.Otherwise, output “0”.input Ainput Binput Coutput YI will generate a validoutput in no more than2 minutes afterseeing valid inputs
13 A Combinational Digital System A system of interconnected elements is combinational ifeach circuit element is combinationalevery input is connected to exactly one output or directly to a source of 0’s or 1’sthe circuit contains no directed cyclesBut, in order to realize digital processing elements we have one more requirement!No feedback (yet!)
14 Noise MarginsKey idea: Don’t allow “0” to be mistaken for a “1” or vice versaUse the same “uniform representation convention”, for every component in our digital systemTo implement devices with high reliability, we outlaw “close calls” via a representation convention which forbids a range of voltages between “0” and “1”.CONSEQUENCE:Notion of “VALID” and “INVALID” logic levelsvoltsForbidden ZoneValid“0”“1”InvalidMin VoltageMax Voltage
15 Digital Processing Elements Some digital processing elements occur so frequently that we give them special names and symbolsI will copy and restore my input to my outputI will output the complement ofmy inputAYAYbufferinverterAANDI will only output a ‘1’ if all myinputs are ‘1’AORI will output a‘1’ if any of myinputs are ‘1’YYBBAXORI will only output a‘1’ if an odd numberof my inputs are ‘1’YB
16 Digital Processing Elements Some digital processing elements occur so frequently that we give them special names and symbolsAYAYbufferinverterAANDAORYYBBAXORIn honor of the richest man in the world we will henceforth refer to digital processing elements as “GATES”YB
17 From What Do We Make Digital Devices? Recall our common thread from Lecture 2…A controllable switch is a common link of all computing technologiesHow do you control voltages with a switch?By creating and opening paths between higher and lower potentialsThis symbol indicates a “high” potential, or the voltage of the power supplyLoadThis symbol indicates a “low” or ground potential
18 N-Channel Field-Effect Transistors (NFETs) When the gate voltage is high, the switch “closes” (connects). Good at pulling things “low”.DD+GGVDS ³ 0+-S-SOperating regions:cut-off:VGS < VTHlinear:VGS ³ VTH VDS < VDsatsaturation:VGS ³ VTH VDS ³ VDsatVGS0.8VIDSSDlinearsaturationSD“VGSVGS - VTHSDVDS
19 P-Channel Field-Effect Transistors (PFETs) When the gate voltage is low, the switch “closes” (connects). Good at pulling things “high”.S-SVGS-+GGVDS 0+DDOperating regions:cut-off:VGS > VTHlinear:VGS VTH VDS > VDsatsaturation:VGS VTH VDS VDsat–0.8VSD-VDS-VGSSD“VGS - VTHsaturationlinearSD-IDS
20 Finally… Using Transistors to Build Logic Gates! We’ll use PFETs hereVDDLogic Gate recipe:pullup: make this connection when VIN is near 0 so that VOUT = VDDVINVOUTpulldown: make this connection when VIN is near VDD so that VOUT = 0and, NFETs here
21 CMOS Inverter Vin Vout A Y Vout Valid “1” Invalid Valid “0” Vin only a narrow rangeof input voltages result in “invalid” output values. (this diagram is greatly exaggerated)Valid “1”Valid “0”InvalidVinVoutVinAYinverter
22 CMOS Complements A A conducts when A is high conducts when A is low What a nice VOH you have...CMOS ComplementsThanks. It runs in the family...AAconducts when A is highconducts when A is lowconducts when A is high and B is high: A.BABconducts when A is low or B is low: A+B = A.BSeries N connections:Parallel P connections:conducts when A is high or B is high: A+BABconducts when A is low and B is low: A.B = A+BParallel N connections:Series P connections:
23 A Two Input Logic Gate A B C 0 0 0 1 1 0 1 1 What function does this gate compute?A B C0 00 11 01 1
24 Here’s Another… A B C 0 0 0 1 1 0 1 1 What function does this gate compute?A B C0 00 11 01 1
25 CMOS Gates Like to Invert OBSERVATION: CMOS gates tend to be inverting!Precisely, one or more “0” inputs are necessary to generate a “1” output, and one or more “1” inputs are necessary to generate a “0” output. Why?AB
26 General CMOS Gate Recipe BCStep 1. Figure out pulldown network that does what you want (i.e the set of conditions where the output is ‘0’) e.g., F = A*(B+C)Step 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnetsABCStep 3. Combine pfet pullup network from Step 2 with nfet pulldownnetwork from Step 1 to form fully-complementary CMOS gate.But isn’t it hard to wireit all up?ABC
27 One Last Exercise Lets construct a gate to compute: F = A+BC = NOT(OR(A,AND(B,C)))VddAStep 1: The pull-down networkBCStep 2: The complementary pull-upnetworkFABC
28 One Last Exercise 1 Lets construct a gate to compute: F = A+BC = NOT(OR(A,AND(B,C)))VddAABCF1Step 1: The pull-down network1Step 2: The complementary pull-upnetworkBCFABCStep 3: Combine and Verify
29 Now We’re Ready to Design Stuff! We need to start somewhere -- usually it’s the functional specificationArgh… I’m tired of word gamesABYIf C is 1 then copy B to Y, otherwise copy A to YCTruth TableIf you are like most engineers you’d rather see a table, or formula than parse a logic puzzle. The fact is, any combinational function can be expressed as a table.These “truth tables” are a concise description of the combinational system’s function. Conversely, any computation performed by a combinational system can expressed as a truth table.
30 Where Do We Start? We have a bag of gates. What do we do? We want to build a computer.What do we do?Did I mention we have gates?We need … a systematic approach for designing logicABLogicGatesF = A xor B
31 A Slight Diversion How many two-input gates are there? Are we sure we have all the gates we need?How many two-input gates are there?Hum… all of these have 2-inputs (no surprise)… 2 inputs have 4 possible valuesHow many possible patterns for 4 outputs are there? ___SURGEANDORNANDNOR24Generalizing, there are 2 , N-input gates!2N
32 There Are Only So Many Gates How many of these gates can be implemented using a single CMOS gate?There are only 16 possible 2-input gates… some we know already, others are just sillyDo we need all of these gates?Nope. After all, we describe them all using AND, OR, and NOT.
33 We Can Make Most Gates Out of Others How many different gates do we really need?B>AXORABYAByABY
34 = = One Will Do! NANDs and NORs are universal Ah!, but what if we want more than 2-inputs==
35 Stupid Gate Tricks DIFFERENT prop delays from each INPUT... 1BCSuppose we have some 2-input XOR gates:tpd = 1And we want an N-input XOR:output = 1 iff number of 1sinput is ODD(“ODD PARITY”)DIFFERENT prop delays from each INPUT...... but we’re taking MAX (worst case).Ntpd = O( ___ ) -- WORST CASE.Can we compute N-input XOR faster?
36 I Think That I Shall Never See a Gate Lovely as a ... 2log2N2k inputsfor k levels.2221log Nlog N2k inputs for k levelslog NN-input TREE has O( ______ ) levels...Signal propagation takes O( _______ ) gate delays.log N
37 Here’s a Design Approach 1) Write out our functional spec as a truth table2) Write down a Boolean expression for every ‘1’ in the output3) Wire up the gates, call it a day, and go home!This approach will always give us logic expressions in a particular form:SUM-OF-PRODUCTSTruth Table-it’s systematic!-it works!-it’s easy! -we get to go home!
38 Straightforward Synthesis We can implementSUM-OF-PRODUCTSwith just three levels oflogic.INVERTERS/AND/ORABCY
40 An Interesting 3-Input Gate Based on C, select the A or B input to be copied to the output Y.Truth TableABYCIf C is 1 then copy B to Y, otherwise copy A to Y2-input MultiplexerABCAYB1GatesymbolCschematic
41 A 4-input Mux (implemented as a tree) MUX ShortcutsA 4-bit wide MuxA 4-input Mux (implemented as a tree)11SA2B2A3B3Y0SA0B0A1B1Y1Y2Y311SI0I1I2I3YS0 S1ABCDS123YA0-3B0-3SY0-3
42 Full-Adder Carry Out Logic Mux Logic SynthesisConsider implementation of some arbitrary Boolean function, F(A,B)... using a MULTIPLEXER as the only circuit element:Full-Adder Carry Out Logic1234567A,B,CinCout1SIMPLE approach for ANY 2-input function:HARD-WIRE Truth Table to a MUX!Variants:DIP SwitchesBlowable FUSESMEMORY CELLS“Select” inputs “ADDRESS” TT Entry.