1. The LHCb Front-end Electronics System Status and Future Development
Ken Wyllie, CERN
On behalf of the LHCb Collaboration
Ken Wyllie
TIPP09

2. Outline The LHCb experiment
Electronics architecture and implementation
Current status
Future plans: the upgrade
Past
Present
Future
Ken Wyllie
TIPP09

3. LHCb: tuned for b-physics
See talk ‘Status of LHCb detector’ by Eric Thomas
Ken Wyllie
TIPP09

4. Electronics Architecture
LHC machine
Calo data
TFC
L0 hardware
trigger
Muon data
DAQ/HLT
ECS
On-detector
Off-detector
Ken Wyllie
TIPP09

5. * See talk ‘The LHCb trigger’ by Hugo Ruiz
LHCb Key Parameters
Bunch crossing rate = 40 MHz
L0 trigger rate = 1 MHz average*
L0 trigger latency = 4 ms fixed (160 BX)*
Event readout time = 900 ns
Event rate to DAQ = 1MHz (35kB event size)
Nominal luminosity = 2 x 1032 cm-2 s-1
Compromise:
Electronics vs
Physics
HLT
L0 hardware
trigger
Calo data
Muon data
Trigger
superviser
* See talk ‘The LHCb trigger’ by Hugo Ruiz
Ken Wyllie
TIPP09

6. L0 Electronics Implementation
Two case studies
Two very different implementations of the same architecture
VELO
(see ‘LHCb vertex locator commissioning’ by Silvia Borghi)
2. RICH
(see ‘The RICH system of LHCb’ by Roger Forty)
Ken Wyllie
TIPP09

7. VELO L0 electronics
Silicon m-strip detectors for precise position resolution
Choice of analog readout:
use pulse-height info to interpolate between strips
can correct for noise problems ‘offline’ (RF pick-up from beam)
172k channels
40MHz analog signal transmission on copper to counting room
Ken Wyllie
TIPP09

8. VELO BEETLE chip
ENC ~ e-/pF
S/N ~ 20 X
Ken Wyllie
TIPP09

9. VELO Readout Vacuum Counting room Repeater Boards Long Kaptons
ADC RX
Buff RX
ADC RX
Buff RX
Analog Data
Copper cables 60m
Ken Wyllie
TIPP09

10. RICH L0 electronics HPDs to detect Cherenkov photons
Pixel device => low noise
Binary readout
Matrix of 32 x 32 pixels/HPD
484 HPDs => 500k channels
Serial data transmission on digital optical link (1.6Gbit/s)
ANODE = Si pixel sensor + readout chip
Ken Wyllie
TIPP09

11. RICH pixel chip 1 bit ! Threshold = 1000e- with 90e- RMS
Two modes: small pixel (62.5mm x 500mm) + slow readout
large pixel (500mm x 500mm) + fast readout (LHCb mode)
Mini pixel circuit
62.5um
500um
Threshold = 1000e- with 90e- RMS
(signal = 5000 e-)
1 bit !
Ken Wyllie
TIPP09

12. L1 electronics 9U modules in crates in counting room
TELL1 module
RX-plugin
Processing
FPGAs
Formatting
FPGA
Output links
9U modules in crates in counting room
Receive data on links from L0 electronics
Processing
@ 1MHz event rate
Fast links into DAQ system
HLT
Ken Wyllie
TIPP09

13. Status of electronics in LHCb
All electronics installed
Commissioning on-going, eg time alignment with
cosmics
fast lasers
tracks from LHC beam dumps
System close to running at 1MHz
Eagerly waiting for return of LHC beam
Ken Wyllie
Ken Wyllie 13
TIPP09
TIPP09

14. Some particles from LHC…
RICH2 in September 2008
VELO in August 2008
Ken Wyllie
Ken Wyllie 14
TIPP09
TIPP09

15. The future: LHCb upgrade
At L = 2 x 1032 cm-2s-1, beyond 5 years of running, statistics don’t improve much
Big statistical improvement if:
increase L to 2 x 1033, AND
improve efficiency of trigger algorithms
BUT current L0 trigger:
rate & latency limited by electronics
BUT…. efficient trigger decisions require
long latencies
computing power
data from many (all) sub-detectors
(momentum, impact parameter .....)
upgrade electronics + DAQ architecture (LHCC )
From LHCC
Ken Wyllie
TIPP09

16. Current vs Upgraded Electronics Architecture
Calo data
Trigger
superviser
L0 hardware
trigger
Muon data
HLT
1MHz
event
rate
Upgrade
Readout
superviser
Hardware
trigger
Data
HLT++
40MHz
event
rate
Read out data from every bunch crossing
Ken Wyllie
TIPP09

17. Upgrade Features Read out detector at 40MHz
later reduced to 30MHz : 1/4 of BXs empty
Implement a ‘rate-control trigger’:
reduces data rate from 40 to 30MHz (‘interaction’ trigger in hardware)
throttle (eg buffer overflows)
allows staging of DAQ
All data arrives at counting room
no hardware trigger decisions sent to front-end
can make online corrections eg spillover in next BX
Ken Wyllie
TIPP09

18. What is required?
Currently, sub-detectors investigating implementation
data bandwidth required
readout architecture (eg analog, binary, digital)
re-using existing front-ends
obsolescence
Some detectors can re-cycle:
eg Outer Tracker, see A.Pellegrino talk
Others have to start again
eg VELO, RICH
replace
re-use
Ken Wyllie
TIPP09

19. R & D: data links Data ~ 30 Tbit/s from detector => ~ 9000 links
LHCb will use the new GigaBit Transceiver (GBT) chipset (common SLHC project)
Radiation tolerant
High bandwidth (user: 3.36 Gbit/s)
Common link for data, fast controls, slow control
Front-end
Back-end
Ken Wyllie
TIPP09

20. On/Off-detector processing
R & D
On/Off-detector processing
Multi-channel ADCs (SAR, 4-5 bits, low power)
40MHz:
Fast algorithms: re-programmable devices?
Radiation tolerance of FPGAs (anti-fuse, flash)
High speed, compact data receivers
(eg parallel optics + FPGAs)
Ken Wyllie
TIPP09

21. Conclusions LHCb tuned for b-physics:
particular constraints on electronics system
Electronics system designed, produced, installed and commissioned
Upgrade architecture is defined: 40MHz readout
R&D now starting
Ken Wyllie
TIPP09