1. SE-3910 Real-time Systems Week 4, Class 1 Quick-Quiz (Ungraded!)
CS2852
5/22/2019
SE-3910 Real-time Systems
Week 4, Class 1
Quick-Quiz (Ungraded!)
Lab 3 due Friday, Week 4
Lab 4 due Tuesday, Week 5
Exams in C
CPU Speed
CPU Utilization
Polling vs. Interrupts
SE3910
Class 2-3
Yoder
PPT notes
Spring 2014
Print 1, 9, 12, 14
Well-Known Ports 20
Generate I/O Materials
Generate Pin Materials
For Tuesday Lab:
Quiz
Lab Safety Checkout
Tentative Class Objectives:
Explain why writing a file causes a pin to “light”
Explain why reading a file reads a 3.3/0V value from a pin
Create programs using file I/O
Create new capabilities for the GPIO library
Create new kernel modules for the BeagleBone?
- Because it’s cool
- To give deeper hardware/software understanding
- To give familiarity with the whole beagle-bone process
Explore the Beaglebone OS source code
Explain key design decisions made by Beaglebone / Linux OS writers
Contrast these decisions with Classic Linux and Windows decisions
Old Stuff:
In-class:
Explain the concept of rise time and fall time.
Make sketch or figure: Using the oscilloscope, measure the time difference between two signals.
For HW/class activity: Classify events as either being synchronous or asynchronous, periodic, aperiodic, or sporadic
Objectives:
Explain the difference between an embedded and non-embedded system
Explain the difference between a real-time system and a non-real-time system
Identify the key components of the Beaglebone platform
Explain why the Beaglebone changes operating frequency under different power conditions
Identify the key hardware interfaces of the beaglebone
Explain the concept of a cape (daughterboard)
Calculate the software GPIO pin number from an expansion port header definition
Understand how to read a basic schematic
Explain the concept of a dropping resistor
Explain the concept of a pull up and a pull down resistor
Short the beaglebone’s output to ground
Connect the input directly to 5V
Connect the input through a resistor to 5V
Discuss peak voltage again
Potential Topics
Piazza
Link to Schilling’s PDF Slides
At end:
Discuss two kinds of interrupt systems:
Idle main
“background” main
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling, Some from Dr. Hornick, etc.
Dr. Yoder

2. Whole-class Quiz! (1) Select all that are real-time systems Video Game
CS2852
5/22/2019
Whole-class Quiz! (1)
Select all that are real-time systems
Video Game
Aircraft Autopilot
Refinery Process Control
Cash Register
Smartphone
Discussion:
Why do we pick these options?
Are there any proceses that are not real-time?
Why does the book re-define real-time systems?
What are the practical implications?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

3. Whole-class Quiz! (2) Select all that are embedded systems Video Game
CS2852
5/22/2019
Whole-class Quiz! (2)
Select all that are embedded systems
Video Game
Aircraft Autopilot
Refinery Process Control
Cash Register
Smartphone
Discussion:
What is the key difference between an embedded system and a non-embedded system?
Does this clarify our answers?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

4. Whole-class Quiz! (3) Where do I find GPIO 49?
CS2852
5/22/2019
Whole-class Quiz! (3) Where do I find GPIO 49?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

5. CPU Speed Fact: Question:
CS2852
5/22/2019
CPU Speed
Fact:
The Beaglebone can operate at 275 MHz, 500 MHz, 600 MHz, or 720 MHz
Question:
Why should I care?
Depending on discussion, model transistor as “capacitor”
Or simply discuss “switching” cost
Switches/s * energy/switch = power (energy/time)
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

6. Tasking What happens when the CPU runs out of tasks to process?
What should I do about it? (Give at least two possible answers.)
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling

7. Utilization Factor Formal Definition How to compute
% non-idle processing
How to compute
ui = ei/pi ei – execution time, worst case
pi – execution period
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling

8. Question How should I set the utilization factor?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling

9. Utilization Factor Theory: See Ch. 3
(from Laplante and Ovaske 4E, p. 12)
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling

10. What is the Zone Type for this system?
CS2852
5/22/2019
A system has 4 processes, as is described below. What is the overall utilization?
Task 1: Measure wheel slip (p1=100ms, e1=12ms)
Task 2: Measure traction capabilities of wheel (p2=50ms, e2=5ms)
Task 3: Monitor system diagnostics (p3=200ms, e3=5ms)
Task 4: Send system messages over network (p4=25ms, e4=1ms)
What is the Zone Type for this system?
Supposing overloaded, how do we fix it?
Also, what other “bottlenecks” might cause us to miss deadlines?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

11. Question while(true) { } How can we make task1() more punctual?
CS2852
5/22/2019
Question
while(true) {
task1()
task2()
task3() }
How can we make task1() more punctual?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

12. Switch de-bouncing How can we avoid multiple presses?
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling

13. (Board code) CS2852 5/22/2019 Do on board. SE-3910 - Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder

14. Interrupt Definitions
CS2852
5/22/2019
Interrupt Definitions
Interrupt
An event in hardware that triggers the processor to jump from its current program counter to a specific point in the code.
Interrupt Service Routine (ISR)
The function that is called or the particular assembly code that is executed when the interrupt happens is called the Interrupt Service Routine (ISR).
Interrupt flag (IFG)
this is the bit that is set that triggers the interrupt, leaving the interrupt resets this flag to the normal state.
Interrupt Enable
Control bit that tells the processor that a particular interrupt should or should not be ignored.
Interrupt Vector Table
A table in memory which maps ISRs to interrupts.
SE Dr. Josiah Yoder
Slide style: Dr. Hornick
Much Material: Dr. Schilling
Dr. Yoder