1. Lava II Mary Sheeran, Koen Claessen Chalmers University of Technology
Satnam Singh, Xilinx

2. Style hints dStudcct a b = outs where ....and2(a,b)...
This is perfectly correct, but it means I have to go looking among the parameters to see which are the circuit inputs. GATHER them into a single structure, which should be last (rightmost) input. Then I can easily tell what the interface of the circuit is.
mycct (a,b) = outs
......

3. Style hints More generally, have circuit parameters as
separate inputs, followed by all circuit inputs in one structure (tuple or list, possibly nested).
”the input”
cctName p1 p2 (a,bs) = (ds,e)
....
used to control generation. For example integer to control size. Or constants for use in the circuit (see next example).
Usually have zero or one parameters.

4. Register reg init (w,din) = dout where dout = delay init m
m = mux (w,(dout,din))

5. Register reg init (w,din) = dout where dout = delay init m
parameter
reg init (w,din) = dout
where
dout = delay init m
m = mux (w,(dout,din))

6. Register Main> reg low (high,high) …. reg init (w,din) = dout where
dout = delay init m
m = mux (w,(dout,din))
Main> reg low (high,high) ….
orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,h
igh],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[hig
h],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[
andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],a
ndl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],del
ay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[h
igh,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[in
v[{Interrupted!}

7. Register This is why we have a two stage process.
First make internal representation in a data type and
THEN simulate or generate formats.
the circuit
Main> simulateSeq (reg low) [(high,low),(low,high),(high,high),(low,high)]
[low,low,low,high]

8. Sequential circuits MUST be simulated using simulateSeq
Main> simulate (reg low) (high,high)
Program error: evaluating a delay component

9. parl f g = halveList ->- (f -|- g) ->- append
Working on lists g f
parl f g = halveList ->- (f -|- g) ->- append

10. two f f f

11. two (two f) f f

12. Many twos
twoN 0 circ = circ
twoN n circ = two (twoN (n-1) circ)

13. unriffle ->- two f ->- riffle
Interleave f f
ilv f
unriffle ->- two f ->- riffle

14. Many interleaves
ilv (ilv (ilv C))

15. Many interleaves ilvN 0 circ = circ
ilvN n circ = ilv (ilvN (n-1) circ)

16. Wiring
id2
swap

17. Butterfly
bfly circ
bfly circ

18. Defining Butterfly bfly 0 circ = id bfly n circ
= ilvN (n-1) circ ->- two (bfly (n-1) circ)

19. Defining Butterfly bfly 0 circ = id bfly n circ
Connection pattern
parameter
circuit
bfly 0 circ = id
bfly n circ
= ilvN (n-1) circ ->- two (bfly (n-1) circ)

20. Another style (matter of taste)
bflly 0 circ as = as
bflly n circ as = os
where
bs = ilvN (n-1) circ as
os = two (bflly (n-1) circ) bs

21. Butterfly Layout on an FPGA

22. mergers and sorters
Can be made recursively from butterfly of two-input two-output comparators on (say) binary or complex numbers, or even on bit-serial numbers. (Batcher’s bitonic sorter)
Such a sorting network is correct if it sorts BITs (theorem known as the 0-1 principle)
Means we can plug in bit-sorters and check the property that the output is always sorted using a SAT-solver or SMV. (Another example of a non-standard component, and of squeezing a difficult problem (integer sorting) into an easier one (bit sorting))

23. Note Could be viewed as Lustre (or similar) embedded in Haskell
Generic circuits and connection patterns easy to describe (the power of Haskell)
Verify FIXED SIZE circuits (squeezing the problem down into an easy enough one)

24. Another example

25. Multiplication
11010
01001
00000

26. Multiplication
msb

27. Multiplication
lsb

28. Structure of multiplier

29. multBin comps (as,bs) = p1:ss
where
([p1]:[p2,p3]:ps) = prods_by_weight (as,bs)
is = redArray comps ps
ss = binaryAdder ([p2,p3]:is)
redArray comps ps = is
(is,[]) = row (compress comps) ([],ps)

30. Reduction tree for multiplier5 4 4 3 3 2
carries
Fast Adder

31. Will concentrate on the reduction tree (a row of compress cells)
Partial products generated using and gates. May also include recoding to reduce size of tree (cf. Booth)

32. Compress (diff=2) n
f-cell
n-2 2

33. n
f-cell
weight w
weight w+1
n-1

34. diff > diff < 2 k k
hcell
wcell
k-1
k+2

35. n
hcell
weight w
weight w+1
n-1

36. n
wcell
weight w
n+1

37. compress comps (as,bs)
| (diff > 2) = (compress comps |- hcell comps) (as,bs)
| (diff == 2) = column (fcell comps) (as,bs)
| (diff < 2) = (compress comps -| wcell comps) (as,bs)
where diff = length bs - length as

39. possible fcell c fullAdd s
halfAdd cells similar. Gives standard array multiplier. Not great!

40. Only need to vary wiring! Make it explicit
fullAdd s c iC s3 cc iS

41. Dadda-like c fullAdd toEnd (a,as) = as++[a] s
Excellent log depth reduction tree , but known for irregularity,
difficult layout

42. picture by Henrik Eriksson, Chalmers

43. Regular reduction tree (Eriksson et al. CE)
fullAdd
toEnd (a,as) = as++[a] s
Nowhere near as good as Dadda, but inspired this work

44. picture by Henrik Eriksson, CE

45. Back to Dadda c fullAdd toEnd (a,as) = as++[a] s
Excellent log depth reduction tree , but known for irregularity,
difficult layout

46. Simple delay analyis (again)
fullAddL [a,b,cc] = [s,c]
where (s,c) = fullAdd (a,(b,cc))
fAddI (a1s, a2s, a3s, a1c, a2c, a3c) [a1,a2,a3]= [s,cout]
where
s = max (a1s+a1) (max (a2s+a2) (a3s+a3))
cout = max (a1c+a1) (max (a2c+a2) (a3c+a3))
fI :: [Signal Int] -> [Signal Int]
fI as = fAddI (20,20,10,10,10,10) as
(Have changed the full-adder interface to be “list to list”.
Was handier in this example.)

47. Checking gate delay comps, tuple of building blocks dDadG n
= simulate(redArray (hI,fI,
toEnd,toEnd,id,splitAt 2,splitAt 3)) (ppzs n)
Gate delay models
wiring cells (allow later inclusion of wiring delay, in next lecture)
(will return to splitAt shortly)

48. Checking gate delay (as before)
Main> dDadG 16
[[0,10],[5,20],[20,30],[30,40],[40,50],[50,50],[50,60],[60,70],[70,70],
[70,70],[70,80],[70,80],[80,90],[90,90],[90,90],[90,90],[90,90],[90,90],
[80,90],[80,80],[70,80],[70,80],[70,70],[60,70],[60,60],[50,60],[50,50],
[40,20],[0,20]]

49. Checking gate delay (as before)
Main> dDadG 54
[[0,10],[5,20],[20,30],[30,40],[40,50],[50,50],[50,60],[60,70],[70,70],[70,70],[70,80],[70,80],[80,90],
[90,90],[90,90],[90,90],[90,100],[90,100],[90,100],[100,110],[110,110],[110,110],[110,110],[110,110],
[110,110],[110,120],[110,120],[110,120],[110,120],[120,120],[120,130],[130,130],[130,130],[130,130],
[130,130],[130,130],[130,130],[130,130],[130,130],[130,140],[130,140],[130,140],[130,140],[130,140],
[140,140],[140,140],[140,150],[150,150],[150,150],[150,150],[150,150],[150,150],[150,150],[150,150],
[150,150],[150,150],[150,150],[150,150],[150,150],[150,150],[140,140],[140,140],[140,140],[140,140],
[140,140],[130,140],[130,140],[130,140],[130,140],[130,140],[130,130],[130,130],[130,130],[130,130],
[130,130],[130,130],[120,120],[120,120],[120,120],[120,120],[110,120],[110,120],[110,120],[110,110],
[110,110],[110,110],[110,110],[100,100],[100,100],[100,100],[90,100],[90,100],[90,90],[90,90],[80,90],
[80,80],[70,80],[70,80],[70,70],[60,70],[60,60],[50,60],[50,50],[40,20],[0,20]]

50. Verifying the multiplier
multDadda (as,bs) = ps
where
ps = multBin(halfAddL,fullAddL,
toEnd,toEnd,id,splitAt 2,splitAt 3)
prop_Equivalent circ1 circ2 a = ok
out1 = circ1 a
out2 = circ2 a
ok = out1 <==> out2

51. Use of predefined Haskell functions
splitAt is a library function from ”the standard prelude”. See
Reading the standard prelude is a good way to learn! Saves
you from reinventing commonly used functions (for example
on lists). Your code gets shorter and easier for me to read.
(Starting from scratch will not be penalised, if correct!)

52. an ordinary Haskell function
Main> :t splitAt
splitAt :: Int -> [a] -> ([a],[a])
Main> splitAt 7 [1..10]
([1,2,3,4,5,6,7],[8,9,10])
Main> splitAt 7 [1..3]
([1,2,3],[])
Main> splitAt 2 [1..10]
([1,2],[3,4,5,6,7,8,9,10])

53. Verifying the multiplier
built-in multiplier
Main> smv (prop_Equivalent multi multDadda)
ERROR - Unresolved overloading
*** Type : Fresh [Signal Bool] => IO ProofResult
*** Expression : smv (prop_Equivalent multi multDadda)
Doesn’t work because we have NOT FIXED the SIZE of the inputs

54. prop_mults mymult n
= forAll (list n) $ \as ->
forAll (list n) $ \bs ->
prop_Equivalent multi mymult (as,bs) OR
multi(as,bs) <==> mymult (as,bs)
Now smv(prop_mults multDadda 8) goes through in less than half a second. But size 16 doesn’t. Why?
See section 4.2 of Lava tutorial (replace verify by smv)

55. The cool thing
The same description with just some different wiring cells gives a GREAT VARIETY of different multipliers
One begins to see some order in the chaos...
The key point was finding the right connection pattern
Ideally, one would like to prove this extremely generic description correct! Open research question....

57. Note
Layout for the Dadda-like tree is no more difficult than for any of the others. Important in practice!
We call it the High Performance Multiplier reduction tree (Henrik, Per, Mary :)
Henrik Eriksson, CE, had first idea and then my mult. descriptions suggested something similar. This led to a layout strategy, which Henrik followed.
Next step is to generate layout from Wired (wire-aware version of Lava)

58. Promising, but we can do better!
Next lecture: circuits that adapt to their surroundings