1. Hong-Hui Chen 05/17/2002 VLSI Design Course
Verilog tutorial
Hong-Hui Chen
05/17/2002
VLSI Design Course

2. Outline What is Verilog? Register transfer level (RTL)
Up_counter example
Test_bench for Up_counter
Get a simulator
Simulation and verification
Synthesis
Back end flow and a real CHIP
Recommended books

3. What is Verilog
Verilog is first introduced in 1984 for Gateway Verilog-XL digital simulator
In 1989, Gateway acquired by Cadence. Then in 1990, Cadence release the Verilog language and Verilog PLI to public.
Open Verilog International(OVI) was formed to maintain the Verilog standard, in 1993, OVI releases the Verilog 2.0 Reference Manual, then becomes the IEEE (Verilog-1995)

4. Register transfer level (RTL)
Elements with memorial ability -> flip-flops -> sequential circuit
Combinational circuit is used to calculate the next state of the flip-flops

5. Up_counter example Four sample designs for up_counter:
up_counter_hello_world.v
up_counter_max.v
up_counter_max_freeze.v
up_counter_max_freeze_pre_load.v

6. Up_counter: in out declaration
module UP_COUNTER_hello_world(clock,reset,value_now);
input clock,reset;
output [7:0]value_now;
reg [7:0]value_now; // Q value for filp-flops ……
endmodule

7. Up_counter: combinational ckt
`ifdef WAY_NO1 // 指定D的方法<1> -> Combinational circuit
wire [7:0]value_now_d; // D values for flip-flops
assign value_now_d=reset?8'b0:(value_now+1'b1);
`else // 指定D的方法<2> -> Combinational circuit
reg [7:0]value_now_d; // D values for flip-flops
or value_now) // sensitivity list
begin
if(reset)
vaule_now_d=8'd0;
else
value_now_d=value_now+1'b1;
end
`endif

8. Up_counter: sequential ckt
A edge triggered always block will infer real flip-flops
clock)
begin
value_now<= value_now_d;
end
Above statement will use 8 flip-flops

9. Up_counter: max module UP_COUNTER_max(clock,reset,max,value_now);
input clock,reset,max;
or value_now or max)
begin
if(reset)
value_now_d=8'd0;
else if(max)
value_now_d=8'd255;
else
value_now_d=value_now+1'b1;
end

10. Up_counter: freeze input clock,reset,max,freeze;
or value_now or max or freeze)
begin
if(reset)
value_now_d=8'd0;
else if(freeze)
value_now_d=value_now; // 把Q又assign給D
else if(max)
value_now_d=8'd255;
else
value_now_d=value_now+1'b1;
end

11. Up_counter: pre_load input clock,reset,max,freeze,pre_load;
input [7:0]pre_load_val;
or value_now or max or freeze or pre_load or pre_load_val)
begin
if(reset)
value_now_d=8'd0;
else if(freeze)
value_now_d=value_now; // 把Q又assign給D
else if(max)
value_now_d=8'd255;
else if(pre_load)
value_now_d=pre_load_val;
else
value_now_d=value_now+1'b1;
end

12. Test_bench for Up_counter
How can we ensure our design is right?

13. Test_bench for Up_counter (1)
`timescale 1ns/1ps
module test_up_counter; // test bench module
reg clock,reset,max,freeze,pre_load;
reg [7:0]pre_load_val;
wire [7:0]value_now;
UP_COUNTER_max_freeze_pre_load MY_COUNTER(clock,reset,max,freeze,pre_load,pre_load_val,value_now);

14. Test_bench for Up_counter (2)
initial
begin
clock=1; reset=1; max=0; freeze=0; pre_load=0; pre_load_val=0;
#81
reset=0;
end
always #10 clock=~clock;
clock) #5
$display("Present valur of the up counter=%d",value_now);

15. The outputs/responses
# Present valur of the up counter= x
# Present valur of the up counter= 0
# Present valur of the up counter= 1
# Present valur of the up counter= 2
# Present valur of the up counter= 3
# Present valur of the up counter= 4

16. Get a simulator (1) Go to the web as figure at right side
Register a new account

17. Get a simulator (2) Put “Download ISE WebPACK” button
ID and password required
Select “Custom” download configuration

18. Get a simulator (3)
Select “MXE Simulator” only -> Download -> Install
In the installation course,
It will remind you to get a license!

19. Fill the form and submit!
Get a simulator (4)
Fill the form and submit!

20. Get a simulator (5)
Please setup the license correctly!

21. Simulation and verification (1)
File -> New -> Project
Copy:
1) Test_up_counter.v
2) Up_counter_max_freeze_pre_load.v to

22. Simulation and verification (2)
Design -> Compile
Select all the
sources
Compile
them!

23. Simulation and verification (3)
Design -> Load Design …
Select the
test bench module

24. Simulation and verification (4)
Execute run 10000ns -> Simulation result is outputted to screen cause $dsiplay() is used in the test bench!

25. Synthesis
Design compiler, Synopsys Inc.

26. Back end flow and a real CHIP
Automatic routing, cell placement, timing analysis
CHIP photo!

27. Recommended books (1) Synthesis issues Beginner’s choice
Chinese copy available
Advanced book
Chinese copy available

28. Recommended books (2)
For CAD designer
CS students