1. Multiplexers
Mux

2. Multiplexer (MUX)
A multiplexer can use addressing bits to select one of several input bits to be the output.
A selector chooses a single data input and passes it to the MUX output
It has one output selected at a time. 2

3. Multiplexers A multiplexer has
N control inputs
2N data inputs
1 output
A multiplexer routes (or connects) the selected data input to the output.
The value of the control inputs determines the data input that is selected.

4. Multiplexer (MUX) Consists of: Inputs (multiple) = 2n Output (single)
Selectors (# depends on # of inputs) = n
Enable (active high or active low)

5. A 2:1 MUX selects input Ii if S0 = I [If S0 = 0, Z = I0
The same can be said about
a 4:1 MUX:
Input Ii is selected (Z=Ii)
if S1S0 combination represents
the number i in binary. Z I1
4:1
MUX I2 I3 S1 S0

6. In general, # of data inputs (Iis) is 2n # of control I/Ps = n
[If S1S0 = 00 (#0), Z = Io
S1S0 = 01 (#1), Z = I1
S1S0 = 10 (#2), Z = I2
S1S0 = 11 (#3), Z = I3]
A generalized or symbolic TT
S1 S Z I0 I1 I2 I3

7. 4 to 1 line multiplexer 4 to 1 line multiplexer 2n MUX to 1
n for this MUX is 2
This means 2 selection lines s0 and s1 S1 S0 F I0 1 I1 I2 I3 7

8. Design of MUXes using Divide-&-Conquer
• A 4:1 MUX can be hierarchically constructed using 2:1 MUXes
Idea: Divide the selection problem by bits of the select/control variables
These inputs should
have different lsb or S0 values, since their sel. is based on S0. All other bits should be equal. I1
2:1
MUX S0 I0 I3 I2 Z S1
MSB
Inputs selected are those w/ the same lsb or S0 values. So further selection needs to be based on the non-lsb bits. I0 Z I1
4:1
MUX I2 I3 S0 S1
These inputs should
have different lsb or S0 values, since their sel. is based on S0. All other bits should be equal.
LSB of control variables

9. Opening up the 8:1 MUX’s hierarchical design
Selected when S0 = 0 I0 I0
2:1
MUX I1
Selected when
S0 = 0, S1 = 1, S2=1 S0
2:1
MUX
8:1
MUX I0 I1 I2 I3 I4 I5 I6 I7
S2 S1 S0 I2 I2
2:1
MUX I2 I6
2:1
MUX I3 S1 Z Z
2:1
MUX S0 I6 S2 I4 I4
2:1
MUX S1 I5 S0
Selected when S0 = 0, S1 = 1. These i/ps should differ in S2 I6 I6
2:1
MUX
These inputs should
have different lsb or S0 values, since their sel. is based on S0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.
These inputs should
have different S1 values, since their sel. is based on S1 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. I7 S0

10. An 8:1 MUX is designed similarly.
Selected when S0 = 0 I0 I0
2:1
MUX I1 S0 I1 I2 I2
2:1
MUX I3
4:1
MUX I0 I1 I2 I3 I4 I5 I6 I7 I3 Z
8:1
MUX I5 S0 Z I4 I4
2:1
MUX I5 S2 S1 S0 I6
S2 S1 S0 I6
2:1
MUX I7 I7
These inputs should
have different lsb or S0 values, since their sel. is based on S0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. S0
Selected when S0 = 1

11. Multiplexers Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
MSB
LSB A B C F I0 1 I1 I2 I3 I4 I5 I6 I7
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

12. Princess Sumaya University
Multiplexers
Digital Logic Design
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MUX Y I0 I1 I2 I3
S1 S0
Dr. Bassam Kahhaleh

13. Princess Sumaya University
Multiplexers
Digital Logic Design
2-to-1 MUX
4-to-1 MUX
MUX Y I0 I1 S
MUX Y I0 I1 I2 I3
S1 S0
Dr. Bassam Kahhaleh

14. Princess Sumaya University
Multiplexers
Digital Logic Design
Quad 2-to-1 MUX x3 x2 x1 x0
MUX Y I0 I1 S y3 y2 y1 y0
MUX A3 A2 A1 A0
S E Y3 Y2 Y1 Y0 B3 B2 B1 B0 S
Dr. Bassam Kahhaleh

15. Princess Sumaya University
Digital Logic Design
Multiplexers
Quad 2-to-1 MUX
MUX A3 A2 A1 A0
S E Y3 Y2 Y1 Y0 B3 B2 B1 B0
Extra Buffers
Dr. Bassam Kahhaleh

16. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y) = ∑(0, 1, 3)
x y F
0 0 1
0 1
1 0
1 1
MUX Y I0 I1 I2 I3
S1 S0 1 F
x y
Dr. Bassam Kahhaleh

17. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y, z) = ∑(1, 2, 6, 7)
MUX Y I0 I1 I2
I3 I4 I5 I6 I7
S2 S1 S0 1
x y z F 1 F
x y z
Dr. Bassam Kahhaleh

18. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y, z) = ∑(1, 2, 6, 7)
x y z F 1
MUX Y I0 I1 I2 I3
S1 S0 z
F = z F z
F = z 1
F = 0
x y
F = 1
Dr. Bassam Kahhaleh

19. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F 1
MUX Y I0 I1 I2
I3 I4 I5 I6 I7
S2 S1 S0 D
F = D D
F = D D
F = D F
F = 0 D
F = 0 1
F = D 1
F = 1
F = 1
A B C
Dr. Bassam Kahhaleh

20. Thank you