1. Chap. 3 Describing Logic Circuits
Chapter Outcomes (Objectives)
Perform the three basic logic operations.
Describe the operation of and construct the truth tables for the AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit.
Draw timing diagrams for the various logic-circuit gates.
Write the Boolean expression for the logic gates and combinations of logic gates.
Implement logic circuits using basic AND, OR, and NOT gates.
Use Boolean algebra to simplify complex logic circuits.
Use DeMorgan’s theorems to simplify logic expressions.
Use either of the universal gates (NAND or NOR) to implement a circuit represented by a Boolean expression.
Explain the advantages of constructing a logic-circuit diagram using the alternate gate symbols versus the standard logic-gate symbols.
Describe the concept of active-LOW and active-HIGH logic signals.

2. Chap. 3 Describing Logic Circuits
Chapter Outcomes (Objectives) – cont.
Describe and measure propagation delay time.
Use several methods to describe the operation of logic circuits.
Interpret simple circuits defined by a hardware description language (HDL).
Explain the difference between an HDL and a computer programming language.
Create an HDL file for a simple logic gate.
Create an HDL file for combinational circuits with intermediate variables.

3. Chap. 3 Describing Logic Circuits
Logic Gates : the basic elements of logic circuits(AND, OR, NOT,...)
Boolean Algebra
A tool for the analysis and design of digital systems
Describes relationship between logic circuit’s inputs and outputs
Used to help simplify a logic circuit
Tab. 3-1
Fig. 3-1
3-1 Boolean constants and
variables
Only two possible values (Many different terms used synonymously)
Logic level 0 Low /1 High
0 and 1 do not present actual numbers but instead represent the state of a voltage variable(High/Low)
3-2 Truth tables
Describing how a logic circuit’s output depends on the logic level of circuit’s input(2N possible inputs)
Fig. 3-1 Truth Table(2, 3, 4 inputs) A B ? x
Tab. 3-1
(a)
(c)
(b)

4. 3-3 OR Operation with OR gates
Output x is a logic 1 if one or more inputs are 1
Boolean expression : x = A + B
x= = 1,
x = = 1,
x = …+ 1 = 1
OR Gate : Fig. 3-2(b)
Multiple input OR Gate : Fig. 3-3
Summary of the OR operation
Exam. 3-1, 3-2, 3-3A, 3-3B
3-4 AND Operation with AND gates
Output x is 1 only when all inputs are 1
Boolean expression : x = AB = A•B
AND Gate : Fig. 3-7(b)
Multiple input AND Gate : Fig. 3-8
Summary of the AND operation
Exam. 3-4, 3-5A, 3-5B
Fig. 3-2(a)
(a)
X= A+B
X= A+B+C A B A B C
(b)
Fig Truth Table and Symbol
Fig Three-input OR
Fig. 3-7(a)
(a)
X= AB
X= ABC A B A B C
(b)
Fig Truth Table and Symbol
Fig Three-input AND

5. 3-6 Describing Logic Circuits Algebraically
3-5 NOT Operation
Single input operation, Complement of input
NOT operation : x= A
NOT circuit : Inverter(Fig. 3-11(b))
App. 3-1 : typical application of NOT gate
(pressed=0, not pressed =1) Fig. 3-12
3-6 Describing Logic Circuits Algebraically
Boolean logic can describe any logic circuit by Boolean expression.
Order of precedence : Parentheses, NOT, AND, OR (Next Slide)
A·B+C can be interpreted in various ways : Fig. 3-13
1) (A·B)+C, 2) A·(B+C)
Circuits containing Inverter : Fig.3-14, Fig.3-15
3-7 Evaluating Logic Circuit Output
Given a Boolean expression
Evaluate output for given inputs
Exam. : Fig. 3-15(a)
A=0, B=1, C=1, D=1, x=0
Exam. : Fig. 3-15(b)
A=0, B=0, C=1, D=1, E=1, x=1
Fig. 3-11(a) 1 A
(a) 1 x
X= A A
(b)
Fig Truth Table, Symbol, waveform

6. Evaluation rule for Boolean expression
1) Perform all inversions of single terms
2) Perform all operations within parentheses
3) Perform an AND operation before an OR operation
4) If an expression has a bar over it, perform the expression first and then invert the result
Determining output level from a diagram
The output can be determined directly from the circuit diagram without using Boolean expression.
Analysis Using a Table
The best way to analyze a combinational logic circuit
Analyze one gate or logic combination at a time
Easily double check your work
Benefit in troubleshooting the logic circuit 1
Fig. 3-15(a) Determining the output from a diagram

7. 3-8 Implementing circuits from Boolean expression
Analysis of a logic circuit using truth tables : Fig. 3-16
1) List all input combinations : A, B, C
2) Create column for each intermediate signal (node) : u, v, w neither inputs nor output
3) Fill the u, v, and w
4) Fill the output x
Exam. 3-6 : Analyze the operation of Fig. 3-15(a)
3-8 Implementing circuits from Boolean expression
Circuit can be implemented from expression
Exam. 3-7 : draw circuit diagram Fig.3-18
Fig Constructing a logic circuit from a Boolean expression

8. 3-9 NOR gates and NAND gates
Exam. 3-8, 3-9
NAND gate :
Exam. 3-10, 3-11, 3-12
3-10 Boolean Theorems
Single variable theorems Fig. 3-25(1)….(8)
x • 0 = 0, x • 1 = x, x • x = x, x • x = 0
x + 0 = x, x + 1 = 1, x + x = x, x + x = 1
Multivariable theorems
x + y = y + x, x•y = y•x
x + (y + z) = (x + y)+ z = x + y + z, x (yz) = (xy)z = xyz,
x (y + z) = xy + xz, (w + x)(y + z) = wy + xy + wz + xz
x + xy = x : P.88 Truth Table or x + xy = x(1+y) = x•1= x
x + xy = x + y : (x + x)•(x + y) = 1 •(x + y) = x + y
Exam. 3-13, 3-14, 3-15
Fig NOR Gate
Fig NAND Gate
Commutative laws
Associative laws
Distributive laws

9.   3-11 DeMorgan’s Theorems DeMorgan’s Theorems Exam. Exam. Exam.
Fig. 3-26, 27 Equivalent circuits implied by DeMorgans Theorems
Exam.
Exam.
Exam.
Exam. 3-16
Exam : Determine the output expression and simplify it
using DeMorgan Theorems

10.       3-12 Universality of NAND and NOR gates
Implement any logic expression using only NAND or NOR gates
Exam : A conveyer belt will shut down whenever specific conditions
occur(x = AB + CD)
74LS00 NAND, 74LS08 AND, 74LS32 OR gate 사용(Fig. 3-31)      
Fig. 3-29, 30 NAND/NOR gates can be used to implement any Boolean operation
Fig Possible implementation

11.      3-13 Alternate Logic-Gate Representations
Standard Logic Symbols : AND, OR, Inverter, NAND, NOR
Alternate Logic Symbols : Fig. 3-33
1) Add bubbles on input and output lines that do not have bubbles, and Remove bubbles that are already there
2) Change the operation symbol from AND to OR, or from OR to AND(Inverter is not changed)
Note:
bubble
no bubble 
The equivalence can be extended to gates with any number of inputs
None of the standard symbols have bubbles on their inputs, but all the alternate symbols have bubbles on their inputs
The standard and alternate symbols for each gate represent the same physical circuit(No differences)
NAND and NOR gates are inverting gates(both the standard and the alternate symbols have a bubble on either the input or the output)
AND and OR gates are non-inverting gates(the alternate symbols have bubbles on both inputs and outputs)    
Fig Standard and alternate symbols

12. 3-14 Which Gate Representation to Use
Logic Symbol Interpretation
Active-HIGH : An input or output line has no bubbles
Active-LOW : An input or output line does have bubbles
Exam : Give the interpretation of the two OR gate symbols
3-14 Which Gate Representation to Use
Proper use of the alternate gate can make the circuit operation much clear: (d) truth table
Active-HIGH
Active-HIGH
Active-LOW
Active-LOW
Output goes LOW only when all inputs are HIGH
Output goes HIGH only when any inputs are LOW
Fig Interpretation of the two NAND gates
Output goes HIGH only when any inputs are HIGH
Output goes LOW only when all inputs are LOW
Fig Interpretation of the two OR gates
Active-HIGH
Active-LOW
Output goes HIGH whenever either A=B=1 or C=D=1
Output goes LOW only when A or B=0 and
C or D=0
(a) original
(b) active high
(c) active low
Fig Alternate Representation

13. Which Circuit Diagram Should be Used?
The answer to this question depends on the particular function being performed by the circuit output
If the circuit is used to turn on/off an LED, Relay, or Motor
Active-HIGH : On when output goes to 1
Active-LOW : On when output goes to 0
Bubble Placement
Whenever possible, choose gate symbols so that
Bubble outputs connected to bubble inputs(Fig (b))
Non-bubble outputs connected to non-bubble inputs(Fig (c))
Exam. 3-20, 21, 22, 23
Asserted Levels
Asserted = Active
Unasserted = Inactive
Labeling Active-LOW Logic Signals
Over-bar = Active Low Signal
Labeling Bi-state Signals
Output signals have two active states
Address Decode 회로

14. 3-15 Propagation Delay
Propagation delay is the time it takes for a system to produce the appropriate output after it receives an input.
An AND gate serves as an example that propagation delay does exist and that it can be measured : Fig. 3-41(a)
Two things are important to note from the timing diagram in Fig. 3-41(b)
Transitions are not truly vertical(instantaneous) so we measure from the % point on the input to the 50% point on the output
The time it takes to make the output to High is not necessarily the same as the time to make the output go Low. These delay times are called t PLH and t PHL : Fig. 8-2
Chapter 8 will provide more information about the inner workings of logic ICs : Fig. 8-8
The speed of a logic circuit is related to this characteristic of propagation delay.
Whatever part is chosen to implement the logic circuit will have a data sheet that states the value of propagation delay : Fig. 8-11

15. IEEE/ANSI standard Logic Symbols
Compare the IEEE/ANSI symbols to traditional symbols
These symbols are not widely accepted but may appear in some schematics.
Symbol descriptions
Rectangular symbols represent logic gates and circuits.
The notation inside symbols show how output depends on inputs.
A small triangle replaces the inversion bubble.
Standard Logic Symbol;
(a) traditional; (b) IEEE/ANSI

16. 3-16 Summary of Methods to Describe Logic Circuits
1. We must be able to represent these logical decisions.
The three basic logic functions are AND, OR, and NOT.
2. We must be able to combine these logic functions and implement a decision-making system.
If it is raining OR it looks like rain I will take an umbrella.
If I get paid AND I go to the bank I will have money to spend.
Seatbelt warning indicator in a car : Exam. 3-24
3-17 Description Languages vs. Programming Languages
HDL – Hardware Description Languages to represent logic circuits.
AHDL – Altera Hardware Description Language (Altera).
VHDL – Very high speed integrated circuit Hardware Description Language (DoD, IEEE).
Hardware Description Languages vs. Programming Languages : Exam. 3-25
Hardware Description Language : to describe the hardware configuration of a circuit (Concurrent)
Programming Language : to represent a sequence of instructions intended to be carried out by a computer to accomplish some task (Sequential)- Fig. 3-43
AND gate
Hardware
AND program

17. 3-18 Implementing Logic Circuits with PLDs : Fig. 3-44
Programmable Logic Devices (PLDs) are devices that can be configured in many ways to perform logic functions.
Internal connections are made electronically to program devices.
1 – connected, 0 – not connected
The hardware description language defines the connections to be made and is loaded into the device after translation by a compiler.
Compiler :
A special application software to translate from the HDL into the grid of 1s and 0s that can be loaded into the PLD.
In details : Fig PLD Basic (next slide)
3-19 HDL Format and Syntax
Languages (interpreted by computers) must follows strict rules of syntax. Syntax refers to the order of elements.
Format refers to a definition of inputs, outputs, and how the output responds to the input (operation). Format of HDL files Fig. 3-46
Inputs and outputs may be called ports (the left & right of Fig. 3-45) – I/O definitions
How the output responds to the input (the middle of Fig. 3-45) – Functional description

18. PLD Basic

19. Boolean Description using AHDL
Figure 3-47 defines an AND gate.
The keyword SUBDESIGN names the circuit block, in this case and_gate
The input and output definitions are enclosed in parenthesis. Variables are separated by commas and follows by :INPUT; / :OUTPUT;.
The logic section is between the BEGIN and END keywords. Operators are: & = AND, # = OR, ! = NOT, $ = XOR
Boolean Description using VHDL
Figure 3-48 defines an AND gate.
The keyword ENTITY names the circuit block, in this case and_gate
The keyword PORT defines the inputs and outputs.
The keyword ARCHITECTURE describes the operation inside the block.
ARCHITECTURE name : ckt
The BEGIN and END contain a description of the operation

20. 3-20 Intermediate Signals
Buried nodes or local signals in HDL are reference points inside a circuit block that are not inputs or outputs. (Signal m in Fig. 3-49)
AHDL Buried Nodes : Fig. 3-50
Keyword VARIABLE defines intermediate signal.
Keyword NODE designates the nature of the variable.
VHDL Local Signals : Fig. 3-51
Keyword SIGNAL defines intermediate signal.
Keyword BIT designates the type of signal